Semiconductor memory device with MOS transistors, each...

Details Semiconductor memory device with MOS transistors, each... Semiconductor memory device with MOS transistors, each...

2007-01-02

2007-01-02

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185050, C365S185130, C365S185280

Reexamination Certificate

active

11111870

ABSTRACT:
A semiconductor memory device includes memory cells, write bit lines, read bit lines, latch circuits, a n-channel MOS transistor, and voltage setting circuits. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. The first MOS transistors are connected commonly to the write bit lines and read bit lines. The latch circuits are provided for the write bit lines and hold write data for the memory cells. The n-channel MOS transistor transfer “1” data to the latch circuits in a data latch operation. The voltage setting circuits supply a potential corresponding to “0” data to the write bit lines in a read operation. In a data latch operation, the latch circuit corresponding to the write bit line connected to the memory cell into which “0” data is to be written latches the potential supplied to the write bit lines in a read operation.

REFERENCES:
patent: 5894437 (1999-04-01), Pellegrini
patent: 6477087 (2002-11-01), Tanaka et al.
patent: 6625063 (2003-09-01), Kim
patent: 6963501 (2005-11-01), Shiga
patent: 7038947 (2006-05-01), Chih
patent: 9-180453 (1997-07-01), None
Wei-Hua Liu, et al., “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Applications”, Non-Volatile Semiconductor Memory Workshop, 4.1, 1997, pp. 1-3.

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