Static information storage and retrieval – Interconnection arrangements – Transistors or diodes
Reexamination Certificate
2005-03-15
2005-03-15
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
Transistors or diodes
C365S134000, C365S203000, C365S207000, C365S214000
Reexamination Certificate
active
06867994
ABSTRACT:
A field region forming a transistor is provided in a direction crossing a word line and a bit line. A bit line contact is provided corresponding to each bit line in a row direction. Storage node contacts are provided in alignment corresponding to respective columns in the row direction. The size of a basic cell region for forming a single memory cell can be set to 2·F·3·F. Here, F represents a minimum design size. Accordingly, memory cells in a twin cell mode DRAM storing one bit of data with two memory cells can be reduced in size.
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McDermott Will & Emery LLP
Nelms David
Pham Ly Duy
Renesas Technology Corp.
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