Semiconductor memory device with memory cell arrays and a redund

Details Semiconductor memory device with memory cell arrays and a redund Semiconductor memory device with memory cell arrays and a redund

1988-07-20

1990-03-13

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Plural blocks or banks

365200, 36518902, G11C 700, G11C 1140

Patent

active

049087983

ABSTRACT:
A semiconductor memory device is provided with a plurality of major memory cell blocks divided into sub-blocks and a redundant memory cell block identical in size with each sub-block. A row decoder circuit as well as two stages of column decoder circuits are provided in association with the major memory cell blocks. Write-in/sense amplifier circuits are located between the two stages of the column decoder circuits and a shifting circuit as well as between the redundant memory cell block and the shifting circuit, so that data bits are amplified after the selection and, then, one of the data bits is replaced with a redundant data bit, if necessary.

REFERENCES:
patent: 4604730 (1986-08-01), Yoshida et al.
patent: 4648075 (1987-03-01), Segawa et al.
patent: 4672581 (1987-06-01), Waller
patent: 4675849 (1987-06-01), Kinoshita

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