Semiconductor memory device with low standby current

Details Semiconductor memory device with low standby current Semiconductor memory device with low standby current

2008-05-16

2010-11-02

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Powering

Data preservation

C365S226000, C365S227000, C365S185240, C365S154000

Reexamination Certificate

active

07826298

ABSTRACT:
In an SRAM according to the present invention, an internal power supply voltage for a memory cell is applied to a back gate of each of P-channel MOS transistors included in an equalizer, a write driver, and a column select gate. Therefore, even if an internal power supply voltage for a peripheral circuit is shut off to reduce current consumption during standby, a threshold voltage of each of the P-channel MOS transistors is maintained at a high level, and hence a leakage current is small.

REFERENCES:
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patent: 7200030 (2007-04-01), Yamaoka et al.
patent: 7362646 (2008-04-01), Otsuka et al.
patent: 7542368 (2009-06-01), Ishikura et al.
patent: 2004/0238875 (2004-12-01), Nakai
patent: 2005-293751 (2005-10-01), None
Yamaoka, Masanao, et al., “A 300 MHz 25 uA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor,” ISSCC 2004/Session 27/SRAM/27.2, 2004.
Yamaoka, Masanao et al., “Low-Power Embedded SRAM Modules with Expanded Margins for Writing,” ISSCC 2005/Session 26/Static Memory/26.4, pp. 480-481, 2005.

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