Semiconductor memory device with low power consumption

Details Semiconductor memory device with low power consumption Semiconductor memory device with low power consumption

2001-08-22

2002-12-03

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S200000, C365S230010, C365S203000, C365S204000, C365S226000

Reexamination Certificate

active

06490221

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device capable of reducing power consumption or to a semiconductor memory device capable of performing a high speed burn-in test.
2. Description of the Background Art
In a prior art DRAM (Dynamic Random Access Memory), a shared sense amplifier configuration is adopted in which sense amplifiers are each shared by adjacent memory cell arrays on both sides thereof as shown in FIG.
21
. Referring to
FIG. 21
, a memory cell array MCAL includes: a plurality of memory cells MCL
1
and MCL
2
; a bit line pair BLL and /BLL; and word lines WL
0
L and WL
1
L. The memory cells MCL
1
and MCL
2
are each constructed of an N channel MOS transistor
151
and a capacitor
152
. The source terminal of the N channel MOS transistor
151
is connected to the bit line BLL or /BLL, the gate terminal thereof is connected to the word line WL
0
L or WL
1
L and the drain terminal is connected to one electrode of the capacitor
152
. The capacitor
152
is provided between the N channel MOS transistor
151
and a terminal
153
and the other electrode (a cell plate electrode) of the capacitor
152
is connected to the terminal
153
. A cell plate voltage Vcp of about half a power source voltage Vcc is supplied to the terminal
153
.
When a high boosted voltage Vpp higher than the power source voltage Vcc is supplied, the word line WL
0
L or WL
1
L is activated to turn on the N channel MOS transistor
151
. By doing so, one electrode of the capacitor
152
is connected to the bit line BLL or /BLL, and an electric charge is supplied to the one electrode of the capacitor
152
from the bit line BLL or /BLL to perform data write, or alternatively an electric charge flows out from the one electrode of the electrode to the bit line BLL or /BLL to perform data read. Hence, the N channel MOS transistor
151
is an access transistor for access to the capacitor
152
in performing data write or data read.
A bit line equalize circuit
160
L is constructed of N channel MOS transistors
161
to
163
. The N channel MOS transistors
161
and
162
are connected in series between the bit line BLL and /BLL, the N channel MOS transistor
163
is connected between the bit lines BLL and /BLL. The N channel MOS transistors
161
to
163
receive a bit line equalize signal BLEQL at each of the gate terminals thereof. When the bit line equalize signal BLEQL is activated, the N channel MOS transistors
161
to
163
are turned on and an intermediate voltage VH supplied to a node
164
between the N channel MOS transistors
161
and
162
is supplied to the bit lines BLL and /BLL to equalize the bit line pair BLL and /BLL to a prescribed voltage. In this case, the N channel MOS transistor
163
exerts a function to equalize a potential on the bit line BLL and a potential on the bit line /BLL.
N channel MOS transistors
190
L and
191
L are both connected between the bit line equalize circuit
160
L and a sense amplifier
170
in series with the respective bit lines BLL and /BLL. The N channel MOS transistors
190
L and
191
L are turned on/off by a bit line select signal BLIL to connect the bit line equalize circuit
160
L and the sense amplifier
170
together.
The sense amplifier
170
is constructed of P channel MOS transistors
171
to
173
; and N channel MOS transistors
174
to
176
. The P channel MOS transistors
172
and
173
are connected in series between the bit lines BLL and /BLL and the N channel MOS transistors
174
and
175
are also connected in series therebetween. The P channel MOS transistor
171
is connected between a power source node
177
and a node
179
A and receives a sense amplifier activating signal SEP at its gate. The N channel MOS transistor
176
is connected between a node
179
B and a ground node
178
and receives a sense amplifier activating signal SEN. The sense amplifier
170
differentially amplifies a potential difference between the bit lines BLL and /BLL.
An IO gate circuit
180
is constructed of N channel MOS transistors
181
and
182
. The N channel MOS transistor
181
connects the bit line BLL and an input/output line IO together and the N channel MOS transistor
182
connects the bit line /BLL and an input/output line /IO together. The N channel MOS transistors
181
and
182
are turned on/off by a column select signal SCL supplied from a terminal
183
.
N channel MOS transistors
190
R and
191
R are both connected between the bit line equalize circuit
160
R and the sense amplifier
170
in series with the respective bit lines BLL and /BLL. N channel MOS transistors
190
R and
191
R are turned on/off by a bit line select signal BLIR to connect the bit line equalize circuit
160
R and the sense amplifier
170
together.
The bit line equalize circuit
160
R has the same configuration as does the bit line equalize circuit
160
L and is activated/deactivated by a bit line equalize signal BLEQR.
A memory cell array MCAR includes memory cells MCR
1
and MCR
2
, a bit line pair BLR and /BLR and word lines WLOR and WL
1
R. Memory cells MCR
1
and MCR
2
have the same configuration as do the memory cell MCL
1
and MCL
2
.
In the configuration shown in
FIG. 21
, when data is inputted/outputted to/from the memory cells MCL
1
and MCL
2
of the memory cell array MCAL, the N channel MOS transistors
190
R and
191
R are turned off by the bit line select signal BLIR while the N channel MOS transistors
190
L and
191
L are turned on by the bit line select signal BLIL. Then, the N channel MOS transistors
181
and
182
are turned on by the activated column select signal SCL and the bit lines BLL and /BLL are connected to the respective input/output lines IO and /IO by the IO gate circuit
180
. Further, the power source voltage and the ground voltage are supplied by the respective sense amplifier activating signals SEP and SEN to activate the sense amplifier
170
. In a standby state, the bit line equalize signal BLEQL is activated and the bit line pair BLL and /BLL are equalized to a precharge voltage. Thereafter, when a memory cycle gets started, the bit line equalize signal BLEQL is deactivated. Subsequent to the deactivation, the word lines WL
0
L and WL
1
L are activated to input/output data to/from the memory cells MCL
1
and MCL
2
. When data input/output finishes, the bit line equalize signal BLEQL is activated to equalize the bit line pair BLL and /BLL to the precharge potential.
Then, when data is inputted/outputted to/from the memory cells MCR
1
and MCR
2
of the memory cell array MCAR, the N channel MOS transistors
190
L and
191
L are turned off by the bit line select signal BLIL, while the N channel MOS transistors
190
R and
191
R are turned on by the bit line select signal BLIR. The N channel MOS transistors
181
and
182
are turned on by an activated column select signal SCL and the bit lines BLR and /BLR are connected to the respective input/output lines IO and /IO by the IO gate circuit
180
. Further, the power source voltage and the ground voltage are supplied by the respective sense amplifier activating signals SEP and SEN to activate the sense amplifier
170
. In the standby state, the bit line equalize signal BLEQR is activated to equalize the bit line pair BLR and /BLR to the precharge voltage. Thereafter, when a memory cycle gets started, the bit line equalize signal BLEQR is deactivated. Subsequent to this deactivation, the word lines WLOR and WL
1
R are activated to input/output data to/from the memory cells MCR
1
and MCR
2
. When data input/output finishes, the bit line equalize signal BLEQR is activated to equalize the bit line pair BLR and /BLR to the precharge potential.
In such a way, in the configuration using shared sense amplifiers, data is alternately inputted/outputted to/from memory cell arrays on both sides of the sense amplifier.
In a highly integrated semiconductor memory device, a chip with a plurality of memory cells arranged in the form of a matrix thereon, all of which cells are in a normal state, is difficult to be fabr

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