Semiconductor memory device with improved read speed

Static information storage and retrieval – Floating gate

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3651851, G11C 1300

Patent

active

059663251

ABSTRACT:
A memory cell of a memory device is constructed such that a source diffusion layer is divided into blocks each containing 16 word lines, and such that a drain diffusion layer is not divided. Each segment of the source diffusion layer is connected to a metal bit line via a block selection MOS transistor. The metal bit line is formed on an insulating film provided on the source diffusion layer so as to be parallel with the source diffusion layer. The block selection MOS transistor is connected to the metal bit line via a contact hole. A gate electrode of the block selection MOS transistor is formed of a polysilicon film for providing a selection gate used to form a word line of the memory cell. A source diffusion layer and a drain diffusion layer of the block selection MOS transistor are formed of the same material as the source diffusion layer of the memory cell and the drain diffusion layer of the memory cell.

REFERENCES:
patent: 5029130 (1991-07-01), Yeh
patent: 5280446 (1994-01-01), Ma et al.
patent: 5687125 (1997-11-01), Kikuchi

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