Semiconductor memory device with high voltage switch

Details Semiconductor memory device with high voltage switch Semiconductor memory device with high voltage switch

1986-08-26

1988-03-22

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365191, 365226, 307571, 307579, G11C 1140, H03K 1710

Patent

active

047333715

ABSTRACT:
A semiconductor memory device according to the present invention includes a first high-voltage switch (20) formed by a first transistor (21), a second transistor (22), a first capacitor (23) and a third transistor (24) and a second high-voltage switch (30) formed by a fourth transistor (31), a fifth transistor (32), a second capacitor (33) and a sixth transistor (34). In a write cycle, input data are stored in capacitors (25, 35). In an erase cycle, the second high-voltage switch (30) is driven by a clock signal (.phi..sub.2) to make the control gate line (4) rise at a high voltage. In a program cycle, the first high-voltage switch (20) is driven by a clock signal (.phi..sub.1) to make the bit line of the bit to be written with data "0" rise at a high voltge, and upon completion of the program cycle, charges stored in the capacitor (25) are discharged to reset a column latch. Thus, the device requires no inverter and may be provided with only one high voltage source.

REFERENCES:
patent: 4506350 (1985-03-01), Asano
patent: 4545038 (1985-10-01), Bellay et al.
patent: 4677313 (1987-06-01), Mimoto
patent: 4689495 (1987-08-01), Liu
ISSCC 83, Feb. 24, 1983, THPM 13.2: A 5 V-Only EEPROM with Intenal Program/Erase Control, pp. 164-165; 302.
ISSCC 83, Feb. 24, 1983, THPM 13.4: +5 V-Only 32K EEPROM, pp. 168 & 169.
ISSCC 85, Feb. 14, 1985, THPM 13.5: A 64K EEPROM with Extended Temperature and Page Mode Operation, pp. 170-171; 336.
ISSCC 85, Feb. 14, 1985, THPM 13.6: Two 35 ns 64K CMOS EEPROMs, pp. 172-173; 337-338.

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