Semiconductor memory device with high speed transmission of addr

Details Semiconductor memory device with high speed transmission of addr Semiconductor memory device with high speed transmission of addr

1992-05-04

1994-01-25

Popek, Joseph A.

Static information storage and retrieval

Addressing

Plural blocks or banks

307443, 307475, G11C 800

Patent

active

052821730

ABSTRACT:
A semiconductor memory device including an address decode signal transmission circuit comprising address buffers; a predecoder; address buses provided before a main decode; a transmission circuit for outputting predecoded signals to the address buses while limiting amplitude thereof; and a receiving circuit provided before the main decoder for differentially amplifying signals from the address buses, wherein the memory cell array is divided into a plural number of sub-blocks and power can be selectively supplied to at least one of the sub-blocks.

REFERENCES:
patent: 4495626 (1985-01-01), Brunin et al.
patent: 5045730 (1991-09-01), Cooperman et al.
patent: 5111080 (1992-05-01), Mizukami et al.
patent: 5227677 (1993-07-01), Furman

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