Semiconductor memory device with high data read rate

Details Semiconductor memory device with high data read rate Semiconductor memory device with high data read rate

1999-04-22

2000-09-26

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

365 72, G11C 800

Patent

active

061250716

ABSTRACT:
A memory cell array has a plurality of memory cells arranged in a matrix. A row decoder has a multiple selection period when a plurality of word lines are simultaneously selected and word lines are sequentially selected. A plurality of sense amplifiers are arranged for each bit line. These sense amplifiers are selectively connected to the bit lines by switch circuits formed on the bit lines. A sense amplifier receives data from memory cells on one bit line through a switch circuit. A plurality of word lines are simultaneously selected and sequentially set at a high level. Data from memory cells on one bit line are sequentially received by the sense amplifier and amplified.

REFERENCES:
patent: 5060230 (1991-10-01), Arimoto et al.
patent: 5793695 (1998-08-01), Kohno
Shigetoshi Wakayama et al.; "10-ns Row Cycle DRAM Using Temporal Data Storage Buffer Architecture" VLSI Circuit Symposium; Jun. 11, 1998.

Affiliated with

Also associated with

Rating

Semiconductor memory device with high data read rate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with high data read rate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with high data read rate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2105890