Semiconductor memory device with flexible configuration

Details Semiconductor memory device with flexible configuration Semiconductor memory device with flexible configuration

1999-08-26

2000-04-04

Mai, Son

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523001, G11C 800

Patent

active

060469579

ABSTRACT:
A semiconductor memory device includes an M-by-N memory array having a number M of complete words, each of the complete words having a number N of bits. The memory array further has M word lines to address the M complete words, and N bit lines to access the N bits. The number N has a number p of integer factors. The memory array can be configured to operate in p different operating modes, where the bits of the complete words are rearranged into at least one sub-word formed as a bit group. An auxiliary address decoder, a mode selector, an auxiliary address router and an input data router cooperate with an input buffer portion of an input/output circuit to enable routing of input data bits from input data lines of an input data bus to a selected sub-word of the memory array. The auxiliary address decoder, the mode selector and an output data router cooperate with an output sense amplifier portion of the input/output circuit to route output data bits of the selected sub-word of the memory array to output data lines of an output data bus.

REFERENCES:
patent: 5307320 (1994-04-01), Farrer et al.
patent: 5406525 (1995-04-01), Nicholes
patent: 5572482 (1996-11-01), Hoshizaki et al.
patent: 5801547 (1998-09-01), Kean
patent: 5978304 (1999-11-01), Crafts

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