Semiconductor memory device with external capacitor to charge pu

Details Semiconductor memory device with external capacitor to charge pu Semiconductor memory device with external capacitor to charge pu

1995-05-25

1996-05-21

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

36518521, 36518514, 36518506, 36518511, 365149, 36518905, 36518909, 365194, 365226, 365228, 365236, 327532, 327534, 327536, G11C 1606

Patent

active

055196543

ABSTRACT:
A semiconductor memory device having a memory cell array with a plurality of transistors (memory cells MC) disposed in a matrix form capable of electrically altering data. In writing data to a plurality of memory cells (MC), a write voltage (V.sub.pp ') is applied to the plurality of memory cells (MC) from a plurality of write circuits (7). The write voltage is generated by boosting an internal voltage (V.sub.CC) by a charge pump circuit (21). In writing data, one of the following methods is used. The plurality of write circuits (7) are sequentially activated by a write control circuit (20) at intervals of delayed timings. The operating point of each memory cell (transistor)(MC) is controlled by operating point control means so as to reduce a current. A capacitor is connected to the output side of the charge pump circuit, and a boosted write voltage is supplied via the capacitor to the write circuit.

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A. Gupta et al., "5-V-only EE-PROM-springboard for autoprogrammable systems", Electronics, Feb. 10, 1982.

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