Semiconductor memory device with error checking and correcting f

Details Semiconductor memory device with error checking and correcting f Semiconductor memory device with error checking and correcting f

1993-05-24

1995-09-12

Trammell, James P.

Excavating

365201, H03M 1300

Patent

active

054504244

ABSTRACT:
A memory cell array is divided into a plurality of subregions along row and column directions. In data reading, 1-bit memory cell is selected from each of the subregions which are arranged on different rows and different columns in this memory cell array. Data are simultaneously read from the simultaneously selected memory cells. The simultaneously read data include information bits and at least one error checking bit. Only data of a 1-bit memory cell is read from one word line at the maximum. Thus, it is possible to extremely reduce a probability that two or more erroneous data bits are included in a plurality of bits of simultaneously read data even if a selected word line is defective. It is possible to execute error checking and correction in accordance with an ECC scheme, improving repairability for defective bits in a semiconductor memory device.

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Ryuji Shibata "1 Mbit Mask Rom and Its Application", Hitachi Review vol. 66 No. 7 (1984-7).

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