Semiconductor memory device with efficient multiplexing of...

Details Semiconductor memory device with efficient multiplexing of... Semiconductor memory device with efficient multiplexing of...

2006-06-06

2006-06-06

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230020

Reexamination Certificate

active

07057964

ABSTRACT:
A semiconductor memory device includes: a memory core area; a plurality of address input pads for transferring addresses; a first address buffer part for receiving the addresses and outputting first addresses; a plurality of multi I/O pads for inputting/outputting data or inputting/outputting addresses/data while multiplexing the addresses/data; a data I/O buffer part for receiving data from the plurality of multi I/O pads and transferring the data to the memory core area or receiving and outputting addresses; a second address buffer part for receiving the addresses from the data I/O buffer part and outputting second addresses; an address multiplexer part for combining the first addresses and the second addresses and outputting data access addresses to the memory core area; and a path control part for controlling the address multiplexer part.

REFERENCES:
patent: 5249160 (1993-09-01), Wu et al.
patent: 6272053 (2001-08-01), Choi
patent: 6507514 (2003-01-01), Tsao et al.
patent: 6687855 (2004-02-01), Krech et al.
patent: 6873563 (2005-03-01), Suwa et al.

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