Semiconductor memory device with dual address memory read amplif

Details Semiconductor memory device with dual address memory read amplif Semiconductor memory device with dual address memory read amplif

1995-06-02

1997-04-08

Nelms, David C.

Static information storage and retrieval

Addressing

Byte or page addressing

36523003, G11C 800

Patent

active

056194730

ABSTRACT:
A semiconductor memory device of the invention includes a memory cell array having a plurality of memory cells, row selector means for selecting a row of the memory cell array corresponding to a row address of an input address, and column selector for selecting a plurality of columns of a memory cell array corresponding to a column address of an input address, and also selecting a plurality of columns of a memory cell array corresponding to at least one column address other than a column address of an input address. The device also includes a sense amplifier for sensing data stored in memory cells. The sense amplifier has at least two sense amplifier groups, the sense amplifier groups sensing data read from a plurality of memory cells corresponding to an input address, and data read from a plurality of memory cells corresponding to the row address of an input address and at least one other column address. The device has a page mode for rapidly switching and outputting data from a plurality of memory cells which have been read in parallel to sense amplifier in accordance with an input address.

REFERENCES:
patent: 5257235 (1993-10-01), Miyamoto
patent: 5293332 (1994-03-01), Shirai
patent: 5305284 (1994-04-01), Iwase
patent: 5398213 (1995-03-01), Yeon

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