Semiconductor memory device with data retention...

Details Semiconductor memory device with data retention... Semiconductor memory device with data retention...

2000-05-31

2001-10-30

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S230030

Reexamination Certificate

active

06310795

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a static semiconductor memory device not requiring a refresh operation.
2. Description of the Background Art
Along with technological advances, electrical equipments are expected to handle more and more information. Accordingly, a semiconductor memory device of a greater capacity is required.
Since one bit of memory cell can be formed by two circuit elements in a dynamic random access memory (DRAM), a DRAM is most suitable for implementing a large capacity semiconductor memory device. On the other hand, a static random access memory (SRAM) excels the DRAM in speed and in power consumption, and is easy to use since no refresh operation is required. As a result, an SRAM is frequently used in a field where performance is a priority, or in a small-scale memory system in which a complex control is not performed. An SRAM normally requires six elements for one bit of memory cell.
In the case of a high-resistance-load cell, four MOS transistors and two high resistance elements form one bit of memory cell.
The large number of elements required per one bit put the SRAM at a great disadvantage in implementing a large capacity semiconductor memory device when compared with a DRAM, however.
To compensate for this disadvantage, an SRAM is proposed in which, instead of providing a high resistance element for data retention, a bit line is precharged and the leakage current flowing through an access transistor is used to retain the data.
FIG. 14
is a block diagram representing the configuration of a conventional semiconductor memory device
501
.
As shown in
FIG. 14
, semiconductor memory device
501
includes a memory array MA containing memory cells M
11
, M
21
, M
31
, and M
41
arranged in a matrix of rows and columns, a word line WL
1
for selecting memory cells M
11
and M
21
, a word line WL
2
for selecting memory cells M
31
and M
41
, bit lines BL
1
and /BL
1
provided corresponding to memory cells M
11
and M
31
, bit lines BL
2
and /BL
2
provided corresponding to memory cells M
21
and M
41
, and a precharging circuit
510
for precharging bit lines BL
1
, /BL
1
, BL
2
, and /BL
2
according to a clock signal T.
Semiconductor memory device
501
further includes a row decode circuit
504
for activating word lines WL
1
and WL
2
according to clock signal T and a row address signal X, a column decode circuit
506
for outputting column select signals DY
1
and DY
2
according to clock signal T and a column address signal Y, a transfer gate circuit
511
for connecting one of bit lines BL
1
and BL
2
to a data line DL and one of bit lines /BL
1
and /BL
2
to a data line /DL according to column select signals DY
1
and DY
2
, and a read/write circuit
508
for writing an input/output data signal DQ into a memory cell according to a write control signal WE during a data write operation and for outputting data read from a memory cell as input/output data signal DQ during a data read operation.
Here, a memory cell array including memory cells arranged in two rows and two columns is shown for simplicity. In practice, a memory cell array includes a greater number of memory cells arranged in a matrix of rows and columns.
FIG. 15
is a circuit diagram showing the configuration of memory cells M
11
and M
31
shown in FIG.
14
.
As shown in
FIG. 15
, memory cell M
11
includes an N-channel MOS transistor
572
connected between bit line BL
1
and a node N
15
and having, a gate connected to word line WL
1
, an N-channel MOS transistor
574
connected between bit line /BL
1
and a node N
16
and having a gate connected to word line WL
1
, an N-channel MOS transistor
576
connected between node N
15
and a ground node and having a gate connected to node N
16
, and an N-channel MOS transistor
578
connected between node N
16
and a ground node and having a gate connected to node N
15
.
N-channel MOS transistors
572
and
574
are referred to as access transistors, and N-channel MOS transistors
576
and
578
are referred to as driver transistors.
Memory cell M
31
includes an N-channel MOS transistor
582
connected between bit line BL
1
and a node N
17
and having a gate connected to word line WTL
2
, an N-channel MOS transistor
584
connected between bit line /BL
1
and a node N
18
and having a gate connected to word line WL
2
, an N-channel MOS transistor
586
connected between node N
17
and a ground node and having a gate connected to node N
18
, and an N-channel MOS transistor
588
connected between node N
18
and a ground node and having a gate connected to node N
17
.
In memory cells M
21
and M
41
shown in
FIG. 14
, bit lines BL
2
and /BL
2
respectively replace bit lines BL
1
and /BL
1
in the configuration of memory cells M
11
and M
31
shown in FIG.
15
. The internal configuration of memory cells M
21
and M
41
are the same as that of memory cells M
11
and M
31
so that the description thereof will not be repeated.
Now, the operation of a conventional semiconductor memory device will be described briefly below.
Referring to
FIGS. 14 and 15
, let us assume that memory cell M
11
retains the data of the logic high or H Level as the potential of node N
15
and that memory cell M
31
retains the data of the logic low or L level as the potential of node N
17
.
While clock signal T is at the L level, all word lines WL
1
and WL
2
and column select signals DY
1
and DY
2
are at a ground potential so that none of the memory cells is selected.
At this time, P-channel MOS transistors
512
to
516
contained in precharging circuit
510
are rendered conductive, and bit lines BL
1
, /BL
1
, BL
2
, and /BL
2
are respectively charged to a power-supply potential.
In addition, the H level data held by node N
15
in memory cell M
11
is retained by the leakage current from N-channel MOS transistor
572
which is an access transistor.
In other words, the potential of node N
15
is determined based on the ratio of the respective resistance values of N-channel MOS transistors
572
and
576
both in the inactive state. If the potential of node N
15
is higher than the threshold voltage of N-channel MOS transistor
578
, node N
16
attains the ground potential, and the data stored in memory cell M
11
is retained.
When clock signal T attains the H level, the read operation begins, and word line WL
1
and column select signal DY
1
attains the H level. Consequently, memory cell M
11
is selected.
When word line WL
1
attains the H level, a current I
1
flows in from bit line /BL
1
into memory cell M
11
. On the other hand, from bit line BL
1
, a leakage current I
2
flows in toward a ground node via N-channel MOS transistor
576
in the inactive state and a leakage current I
3
flows into the unselected memory cell M
31
. The sum of these leakage currents is sufficiently smaller than the current that flows into memory cell M
11
from bit line /BL
1
. Therefore, a potential difference is generated between bit lines BL
1
and /BL
1
. This potential difference is amplified by read/write circuit
508
and is output to the outside as input/output data signal DQ.
When clock signal T once again attains the L level, the access to the memory cell is completed.
Once again, all word lines WL
1
and WL
2
and column select signals DY
1
and DY
2
attain the ground potential. Bit lines BL
1
, /BL
1
, BL
2
, and /BL
2
are charged by precharging circuit
510
, and the H level data held by node N
15
in memory cell M
11
is also charged by the leakage current from N-channel MOS transistor
572
which is an access transistor.
By precharging a bit line in order advantageously to utilize the leakage current from an access transistor for data retention, a memory cell of an SRAM can be configured with four elements. As a result, an SRAM of a larger capacity than that having a memory cell configured with six elements can be easily produced. In addition, since no refresh operation as required by a DRAM is necessary, an easy-to-use SRAM can be provided.

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