Semiconductor memory device with column-wise signal access

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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36523008, 365239, G11C 800

Patent

active

052726789

ABSTRACT:
A semiconductor memory device according to the present invention has data reading lines provided corresponding to word lines, second switches disposed between memory cells and the data reading lines to deliver data onto the data reading lines in accordance with a column address signal, and a column address generating circuit for generating an address signal. With this arrangement, it is possible to read out data stored in the memory cells arranged in a column-wise direction at increased speed. Further it is possible to eliminate a shift circuit, a shift value control circuit, a register and an input control circuit which are needed in conventional semiconductor memory devices to read the data from memory cells arranged in a column-wise direction, thereby reducing the scale of the circuit arrangement.

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patent: 4723228 (1988-02-01), Shah et al.
patent: 4839868 (1989-06-01), Sato et al.
patent: 4896294 (1990-01-01), Shimizu et al.
patent: 4982372 (1991-01-01), Matsuo
patent: 4985867 (1991-01-01), Ishii et al.

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