Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-06-05
2001-09-11
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S149000, C257S296000, C257S369000
Reexamination Certificate
active
06288927
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, more particularly to an improvement in a sense amplifier of a DRAM.
In company with a recent increase in an operating speed of a microprocessor, a high speed semiconductor memory has been demanded. The advent of a large capacity semiconductor memory and popularization of a portable gadget has further necessitated low power consumption to be realized. It is effective to reduce a bitline capacitance in order to materialize a higher speed device with lower power consumption and various techniques for the purpose have conventionally been contrived.
As main factors constituting a bitline capacitance, there are named: a bitline capacitance with other wirings (including an adjacent bitline) and a diffusion capacitance in a contact portion of a bitline with a diffusion region (hereinafter referred to as bitline contact). The bitline contact is in a broad sense divided into a contact to a diffusion region of a memory cell transistor and contacts in. a transfer gate, a bitline equalizer, a column gate and a sense amplifier, which constitute a sense amplifier section. Since each of circuits constituting the sense amplifier section has conventionally been constructed by an independent element pattern, a bitline contact has been required to be provided for each circuit.
As described above, since a bitline contact has conventionally provided for each circuit constituting the sense amplifier section, it has been difficult to reduce a bitline capacitance and it is, therefore, hard to realized a device with a high speed and low power consumption.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device in which the number of bitline contacts in a sense amplifier section is reduced to decrease a bitline capacitance and thereby low power consumption and a high speed operation are realized.
A semiconductor memory device according to the present invention comprises: a semiconductor substrate; and a plurality of element regions formed in the semiconductor, wherein at least one column gate and at least one equalizer are formed as a set in one element region of the plurality of element regions.
Preferred embodiments of the present invention are as follows:
(1) At least two sets of the column gate and the equalizer are formed in one element region and a set of the column gate and the equalizer shares a diffusion layer with an adjacent set of the column gate and the equalizer.
(2) A gate electrode of the equalizer is disposed so as to divide a diffusion layer region into six regions.
(3) Circuit constitution is mainly considered, the column gate comprises: a first transistor, a gate of the first transistor being connected to a column gate select line, one of a source and a drain of the first transistor being connected to a first data line and the other being connected to a first bitline; and a second transistor, a gate of the second transistor being connected to the column gate select line, one of a source and a drain of the second transistor being connected to a second data line and the other being connected to a second bitline, and the equalizer comprises: a third transistor a gate of the third transistor being connected to an equalizer control line one of a source and a drain of the third transistor being connected to the first bitline and the other being connected to an equalizer voltage supply line; a fourth transistor, a gate of the fourth transistor being connected to the equalizer control line, one of a source and a drain of the fourth transistor being connected to the second bitline and the other being connected to the equalizer voltage supply line; and a fifth transistor, a gate of the fifth transistor being connected to the equalizer control line, one of a source and a drain of the fifth transistor being connected to the first bitline and the other being connected to the second bitline, wherein the other of a source and drain of the first transistor, one of a source and drain of the third transistor and one of a source and drain of the fifth transistor are connected to the first bitline through a common contact and the other of a source and drain of the second transistor, one of a source and drain of the fourth transistor and the other of a source and drain of the fifth transistor are connected to the second bitline through a common contact.
(4) Configuration of transistor is mainly considered, the column gate comprises first and second column gates; the equalizer comprises first and second equalizers; the first column gate comprises first and second transistors; the first equalizer comprises: a third transistor having a first common node in common owned by the first transistor; a fourth transistor having a second common node in common owned by the second transistor; and a fifth transistor having the first and second common nodes; the second column gate comprises sixth and seventh transistors; the second equalizer comprises: an eighth transistor having a third common node in common owned by the sixth transistor; a ninth transistor having a fourth common node in common owned by the seventh transistor; and a tenth transistor having the third and fourth common nodes.
(5) In (4), the one element region comprises the first and second sets of the column gate and the equalizer formed therein in an adjacent manner, wherein diffusion layers of the first and second transistors of the first column gate of the first set are shared by diffusion layers of the sixth and seventh transistors of the second column of the second set.
(6) In (5), the shared diffusion layer is provided with a contact and the gate electrode of the column gate is disposed so as to surround the equalizer.
(7) In (5) or (6), a first set and a second set of the column gate and the equalizer is disposed parallel to a bitline.
(8) In (7), a equalizer control line is disposed normal to the bitline, and the equalizer control line is made of an upper wiring layer than a wiring layer of the bitline.
(9) In (8), at least one bitline precharge voltage supply line is disposed between the first set and the second set disposed in an adjacent manner, the bitline precharge voltage supply line is disposed normal to the bitline, and the bitline precharge voltage supply line is made of an upper wiring layer than a wiring layer of the bitline.
(10) In (8), at least two bitline precharge voltage supply lines are disposed normal to the bitline.
(11) In (10), at least one bitline precharge voltage supply line is disposed at both ends of the first and second sets, which are disposed in an adjacent manner, in a direction parallel to the bitline.
(12) In (10), at least one bitline precharge voltage supply line is disposed at both ends of each of the first and second sets, which are disposed in an adjacent manner, in a direction parallel to the bitline.
(13) In (7), gate electrodes of the equalizers included in a first set and a second set disposed in an adjacent manner are connected to by a common gate wiring.
(14) In (5), the first transistor comprises: a first diffusion region; a second diffusion region, which constitutes the second common node; and a first gate electrode, which is provided between the first and second diffusion regions; the second transistor comprises: a third diffusion region; a fourth diffusion region, which constitutes the second common node; a second gate electrode, which is provided between the third and fourth diffusion regions; the third transistor comprises: the second diffusion region; a fifth diffusion region; a third gate electrode, which is provided between the second and fifth diffusion regions; the fourth transistor comprises: the fourth diffusion region; a sixth diffusion region; a fourth gate electrode, which is provided between the fourth and six diffusion regions; the fifth transistor comprises: the second diffusion region; the fourth diffusion region; a fifth gate electrode, which is provided between the second and fourth diffusion regions; the sixth transistor comprises:
Inaba Tsuneo
Shiratake Shinichiro
Tsuchida Kouji
Banner & Witcoff , Ltd.
Ho Hoai V.
Kabushiki Kaisha Toshiba
LandOfFree
Semiconductor memory device with column gate and equalizer... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device with column gate and equalizer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with column gate and equalizer... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2435379