Semiconductor memory device with changeable input/output data bi

Details Semiconductor memory device with changeable input/output data bi Semiconductor memory device with changeable input/output data bi

1993-11-22

1995-03-21

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

365230030, 365230050, 365195, G11C 800

Patent

active

054002923

ABSTRACT:
A dynamic type semiconductor memory device includes a plurality of data input/output nodes, a plurality of /CAS buffers for generating column address strobe signals corresponding to each of said input/output nodes, and an input node carrying out only data input. A switching signal generation circuit generates first and second switching signals indicating data input/output control modes. Memory cells corresponding in number to the data input/output nodes are selected simultaneously from a memory cell array. In operation of control mode A, data input/output is effected using an input node and one data input/ouput node. In the case of control mode B, data writing/reading is effected via a plurality of data input/output nodes according to one column address strobe signal. In the case of control mode C, data input/output is carried out individually for each input/output node according to a plurality of column address strobe signals. Modes A, B and C can be realized in one DRAM. Particularly, in mode C controlling data input/output according to respective column address strobe signals, writing/reading of unnecessary data bits can be prevented to reduce power consumption and prevent erroneous parity bit writing.

REFERENCES:
patent: 4989185 (1991-01-01), Matsuo et al.
patent: 5053999 (1991-10-01), Matsumura et al.
patent: 5243560 (1993-09-01), Amishiro et al.
patent: 5260895 (1993-11-01), Shishikura
patent: 5295108 (1994-03-01), Higa

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