Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
1999-04-09
2001-09-18
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S529000
Reexamination Certificate
active
06291844
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundancy circuit.
The redundancy circuit has been used in a semiconductor memory device such as a dynamic random access memory device and a static random access memory device for remedy of defective devices for improvement in yield of the devices. The redundancy circuit is incorporated with a large number of fuses for redundancy remedy programming. Those fuses are provided on a predetermined region where a window is formed so that a laser beam is irradiated through a window onto the fuse to cut the fuse, for which reason any interconnections are prevented from extending through the window region. It is impossible that the fuses are formed under the interconnection layers for reduction in area of the chip. This provides a limitation to reduce the chip size.
In recent years, the scaling up of the memory cells have been improved due to development in scaling down of the transistors and interconnections to be integrated, whereby the redundancy circuit scale is also increased. As compared to the development in design techniques of the transistors and interconnections, the development speed of the fuse pitch design rule is slower, whereby the occupied area of the redundancy circuit is increased. This is one of the serious problem in realizing a possible chip size shrinkage.
FIG. 1
is a plan view illustrative of a conventional layout of a semiconductor memory device having cell plates and fuses. The semiconductor memory device
21
has four plates, bonding pads
24
,
25
and sets of fuses
23
provided between adjacent two cell plates
22
. The region where the fuses
23
are provided have windows. The programming of the redundancy circuit is carried out by irradiation of the laser through the window onto the fuses. This window region has no interconnections. Namely, any interconnections are required to extend to avoid this window regions having the fuses
23
. This provides the limitation of the freedom in design of the layout of the interconnections.
In the above circumstances, it has been required to develop a novel layout of fuses in the redundancy circuits for enabling the chip size to be reduced.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel semiconductor memory device free from the above problems.
It is a further object of the present invention to provide a novel semiconductor memory device having a redundancy circuit with an improved fuse layout for enabling the chip size to be reduced.
The first present invention provides a layout of fuses for programming a redundancy circuit in a semiconductor device, wherein the fuses are aligned to form at least one straight line which corresponds to at least one alignment of a plurality of bonding pads.
The second present invention provides a layout of at least one line-shaped fuse window showing fuses for programming a redundancy circuit in a semiconductor device, wherein the at least one line-shaped fuse has a longitudinal direction which corresponds to at least one alignment of a plurality of bonding pads.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
REFERENCES:
patent: 5015989 (1991-05-01), Wohlfarth et al.
patent: 5594273 (1997-01-01), Dasse et al.
patent: 61-241943 (1986-10-01), None
patent: 5-243387 (1993-09-01), None
Crane Sara
NEC Corporation
Young & Thompson
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