Static information storage and retrieval – Addressing – Sync/clocking
Patent
1993-02-26
1996-10-15
Nelms, David C.
Static information storage and retrieval
Addressing
Sync/clocking
327 10, 327 16, 327 36, 327174, 327217, G11C 800
Patent
active
055661297
ABSTRACT:
A semiconductor memory device with an address transition detector comprises a flip-flop circuit (FF) having set and reset input terminals and a delay circuit (3). A pulse signal is input to a set input terminal (S) of the flip-flop circuit (FF) and an output signal (P) of the flip-flop circuit (FF) is input through the delay circuit (3) to a reset terminal (R) of the flip-flop circuit (FF), whereby a constant width signal which is independent of a waveform of an address signal and which responds only to the change of address can be obtained as an address transition signal of a SRAM (static random access memory). An internal circuit of the SRAM is initialized by the constant width signal, thereby preventing a malfunction caused by the fact that an initialization time depends on the waveform of the address signal.
REFERENCES:
patent: 5059818 (1991-10-01), Witt et al.
patent: 5233232 (1993-08-01), Steubing et al.
patent: 5255130 (1993-10-01), Buchan et al.
Kohri Shumpei
Nakagawara Akira
Nakashima Katsuya
Nelms David C.
Niranjan F.
Sony Corporation
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