Static information storage and retrieval – Addressing – Sync/clocking
Patent
1996-09-13
1998-11-03
Popek, Joseph A.
Static information storage and retrieval
Addressing
Sync/clocking
36523006, G11C 800
Patent
active
058319301
ABSTRACT:
A semiconductor memory device includes a plurality of memory cells for storing data and a selector for selecting at least one memory cell from the plurality of memory cells based on an address signal. The semiconductor memory device includes a transient detecting unit for outputting a first signal in accordance with a transient of the address signal; and a generator for generating a second signal indicating a wait for accessing a memory cell based on the first signal and a clock signal.
REFERENCES:
patent: 4271487 (1981-06-01), Craycraft et al.
patent: 4581718 (1986-04-01), Oishi
patent: 4710648 (1987-12-01), Hanamura et al.
patent: 4744063 (1988-05-01), Ohtani et al.
patent: 4922122 (1990-05-01), Dubujet
patent: 5159574 (1992-10-01), Kim et al.
patent: 5264737 (1993-11-01), Oikawa
patent: 5305284 (1994-04-01), Iwase
patent: 5313436 (1994-05-01), Matsubishi
patent: 5483498 (1996-01-01), Hotta
Popek Joseph A.
Sharp Kabushiki Kaisha
Tran Michael T.
LandOfFree
Semiconductor memory device with address signal transition detec does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device with address signal transition detec, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with address signal transition detec will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-697731