Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Reexamination Certificate
2000-12-22
2002-06-11
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
C257S296000, C257S390000, C257S544000
Reexamination Certificate
active
06404036
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a DRAM with a triple well structure, and more particularly to a layout of a memory cell sub-array for a DRAM with a triple well structure.
For designing masks of the memory device, a high integration of the device is one of the important issues. It is the most important issue how to suppress the chip size with satisfying the requirement for the high integration.
The DRAM has the triple well structure and double-layered interconnections, wherein a top interconnection layer serves as a signal interconnection layer whilst a bottom interconnection layer serves as a power or ground layer.
FIG. 1A
is a fragmentary plane view illustrative of the conventional triple well structure for DRAM.
FIG. 1B
is a fragmentary cross sectional elevation view illustrative of the conventional triple well structure for DRAM taken along a B-B′ line of FIG.
1
A. An n-type deep well region
2
is selectively formed in a cell array formation region of a p-type semiconductor substrate
1
. A p-type shallow well region
3
is formed in a shallow region of the p-type semiconductor substrate
1
. N-type isolation well regions
4
extend to surround a part of the p-type shallow well region
3
and isolates the part of the p-type shallow well region
3
from the p-type semiconductor substrate
1
. The isolation well regions
4
reach the peripheral regions of the n-type deep well region
2
. A memory cell and an n-channel transistor are formed in the defined p-type shallow well region
3
. A p-channel transistor is formed in the n-type isolation well regions
4
.
FIG. 2
is a fragmentary plane view illustrative of a cell array block having the conventional triple well structure shown in
FIGS. 1A and 1B
. In order to shrink a cell array block
200
, a p-channel transistor SAP
241
is formed in a left side region of the n-type isolation well regions
204
, whilst a p-channel transistor SAP
244
is formed in a right side region of the n-type isolation well regions
204
. A memory cell array block
200
is accommodated in the p-type well
203
. A p-channel transistor SAP
241
(sense amplifier bank p-type transistor) for a sense amplifier bank
240
is formed in the left side region of the n-type isolation well regions
204
which are positioned in both sides of the p-well
203
, in order to shrink the chip size.
FIG. 3A
is a fragmentary enlarged plane view illustrative of the left side region of the cell array block shown in FIG.
2
.
FIG. 3B
is a fragmentary enlarged cross sectional elevation view taken along a C-C′ line of FIG.
3
A.
This layout, however, causes a disadvantage that the provision of the p-channel transistor SAP
241
in the left side region of the n-type isolation well regions
204
causes that a VINT
2
AL line
209
(a voltage feeding line internally by 2
nd
aluminum VINT
2
AL
209
) necessary for the p-channel transistors SAP
241
-SAP
244
extends to reach the left side edge, whereby an interconnection SA
2
AL
210
′ connected with a GND line SA
2
AL
210
extends beyond the n-type isolation well regions
204
which defines the cell array block
200
. This means that no substantive shrinkage can be obtained.
In the above circumstances, it had been required to develop a novel layout for DRAM free from the above problem.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel layout for DRAM free from the above problems.
It is a further object of the present invention to provide a novel layout for DRAM having a triple well structure and double layered interconnections, wherein a bottom interconnection serves as a signal interconnection, whilst a top interconnection serves as a power line or a ground line, wherein the layout is optimum to realize a possible shrinkage by preventing and avoiding that the internal power feeding line and the ground line extend belong the peripheral region of the cell array block.
It is a still further object of the present invention to provide a novel semiconductor memory device free from the above problems.
It is yet a further object of the present invention to provide a novel semiconductor memory device having a triple well structure and double layered interconnections, wherein a bottom interconnection serves as a signal interconnection, whilst a top interconnection serves as a power line or a ground line, wherein the layout is optimum to realize a possible shrinkage by preventing and avoiding that the internal power feeding line and the ground line extend belong the peripheral region of the cell array block.
The present invention provides a layout structure of an interconnection which feeds a fixed voltage level to a sense amplifier provided in a cell array block of a semiconductor memory device, wherein the interconnection selectively extends only an inside of an outside edge of a second conductivity type outside well region provided along one peripheral side of a first conductivity type well region, in which the cell array block is provided.
The present invention also provides a layout structure of a sense amplifier bank provided outside of a memory cell region of a semiconductor memory device, wherein the sense amplifier bank selectively extends both a first conductivity type sub-well region and an adjacent first side region of a second conductivity type isolation well which defines a memory cell region, and the first conductivity type sub-well region is defined between a second conductivity type outside well region and the first side region of the second conductivity type isolation well.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
REFERENCES:
patent: 5455437 (1995-10-01), Komori et al.
patent: 6208010 (2001-03-01), Nakazato et al.
patent: 6285240 (2001-09-01), Shiau et al.
Wilson Allan R.
Young & Thompson
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