Semiconductor memory device with a stacked gate including a...

Details Semiconductor memory device with a stacked gate including a... Semiconductor memory device with a stacked gate including a...

2006-10-10

2006-10-10

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185330

Reexamination Certificate

active

07120057

ABSTRACT:
A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another, memory cells each of which includes a first MOS transistor formed on the first semiconductor layer, a second and a third MOS transistor which are formed on the second and third semiconductor layers, respectively, a first metal wiring layer which connects the gate of the first MOS transistor to the source or drain of at least one of the second and third MOS transistors, and a first contact plug which connects the fourth semiconductor layer to the first metal wiring layer. The first wiring layer is in the lowest layer of the metal wiring lines connected to the gate of the first MOS transistor.

REFERENCES:
patent: 6483749 (2002-11-01), Choi et al.
patent: 2000-332202 (2000-11-01), None
Tomasz Brozek “Effect of Device Type and Plasma Process on the Oxide Thickness Dependence of Plasma-Induced Charging Damage”, International Symposium on Plasma Process-Induced Damage, 1998, pp. 46-49.
Barry P. Linder, et al., “Calculating Plasma Damage as a Function of Gate Oxide Thickness”, International Symposium on Plasma Process-Induced Damage, 1998, pp. 42-45.
Wei-Hua Liu, et al., “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Applications”, NVSMW 4.1, Feb. 1997, pp. 1-3.

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