Semiconductor memory device with a stacked capacitance...

Details Semiconductor memory device with a stacked capacitance... Semiconductor memory device with a stacked capacitance...

1998-07-07

2001-06-19

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S385000, C257S774000

Reexamination Certificate

active

06249054

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a semiconductor Dynamic Random Access Memory (DRAM) device each memory cell of which has a stacked-capacitor structure, and a fabrication method of the device.
2. Description of the Prior Art
In recent years, the memory cell of a DRAM has been miniaturized more and more from generation to generation. Even if the memory cell is minimized, a specific charge is essentially stored in the storage capacitor of the cell to store the information.
The obtainable capacitance of the storage capacitor tends to decrease dependent upon the level of the miniaturization of the storage cell. On the other hand, the necessary capacitance of the capacitor is almost constant when the storing voltage to be applied across the capacitor is fixed. Therefore, it is necessary for the capacitor to compensate the capacitance decrease due to the miniaturization by, for example, increasing the surface area of the capacitor. This surface area increase has been popularly realized by increasing the thickness of the lower electrode (or, storage electrode) of the capacitor.
However, the thickness increase of the lower or storage electrode of the capacitor causes an excessive height difference between the memory cell area where the memory cells are arranged in a matrix array and the peripheral circuit area where the peripheral logic circuits for driving the memory cells are formed. As a result, an aluminum (Al) wiring layer which is formed over the memory cell area and the peripheral circuit area tends to have some excessively thin parts and/or to be partially broken.
Also, in the patterning step of the wiring layer, a photoresist film on the aluminum layer is patterned by using a photolithography process to thereby form an etching mask. The increased overall height of the capacitor causes an excessive focal point shift between the area located over the capacitor and the remaining area during the photolithography process. As a result, the patterning accuracy of the wiring layer will degrade.
The height difference noted above can be relaxed or decreased by, for example, forming a thick interlayer insulating layer to cover the storage capacitors over the entire semiconductor substrate and then planarizing the surface of the interlayer insulating layer thus formed by a thermal reflowing process or Chemical-Mechanical Polishing (CMP) process. However, the thick interlayer insulating layer will cause another problem of disconnection or breaking of the aluminum wiring layer within contact holes. The reason is that the contact holes formed through the thick interlayer insulating layer have a large aspect ratio, which is defined as a ratio of the height of the holes with respect to the width/diameter of the holes. This results in degradation in step coverage of the aluminum wiring layer.
Then, to solve the above problem of disconnection or breaking of the aluminum wiring layer within the contact holes, an improved conventional structure where conductive pads for the capacitors are formed by using a conductive layer for forming the lower storage electrode of the capacitor was proposed. This conventional structure was disclosed in the Japanese Non-Examined Patent Publication No. 3-270168 published in December 1991.
The fabrication method of the conventional structure of the DRAM is explained below with reference to
FIGS. 1A
to
1
F.
It is needless to say that this conventional DRAM has a lot of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and a lot of stacked capacitors in a memory cell area and a lot of MOSFETs in a peripheral circuit area. However, for the sake of simplification of description, only two of the MOSFETs and only two of the corresponding capacitors in the memory cell area and only one of the MOSFETs in the peripheral circuit area are explained here.
First, as shown in
FIG. 1A
, a field oxide layer
102
is selectively formed on a main surface of a p-type single-crystal silicon (Si) substrate
101
by a popular LOcal Oxidation of Silicon (LOCOS) process, thereby defining active regions in the surface area of the substrate
101
in the memory cell area A
1
and the peripheral circuit area A
2
. The main surface of the substrate
101
is exposed from the field oxide layer
102
in the active regions.
Next, after impurity ions are selectively implanted into the active regions to adjust the threshold voltage of the MOSFETs, gate oxide layers
103
are selectively formed on the main surface of the substrate
101
in the respective active regions. An n-type polysilicon layer with a thickness of approximately 300 nm, which is doped with phosphorus (P), is formed over the entire substrate
101
by a popular Chemical Vapor Deposition (CVD) process. The n-type polysilicon layer is then patterned to form gate electrodes
104
on the corresponding gate oxide layers
103
, and gate electrodes
104
A on the field oxide layer
102
.
Subsequently, using the gate electrodes
104
and the field oxide layer
102
as a mask, the active regions of the substrate
101
are selectively ion-implanted with phosphorus (P) with a dose of approximately 2×10
13
atoms/cm
2
, thereby forming n
−
-type diffusion regions
105
used for source/drain regions of the MOSFETs. A layer of High-Temperature Oxide (HTO) of silicon is formed over the entire substrate
101
by a Low-Pressure CVD (LPCVD) process and is etched back by an anisotropic etching process, thereby forming sidewall spacers
106
on the exposed main surface of the substrate
101
and sidewall spacers
106
A on the field oxide layer
102
at each side of the respective gate electrodes
104
.
Next, using a patterned photoresist film (not shown), the sidewall spacers
106
and the gate electrodes
104
as a mask, the active regions of the substrate
101
in the peripheral circuit area A
2
are selectively ion-implanted with arsenic (As) with a dose of approximately 3×10
15
atoms/cm
2
, thereby forming n
−
-type diffusion regions
107
used for source/drain regions of the MOSFETs. Thus, Lightly-Doped Drain (LDD) structures are formed in the active regions for the n-channel MOSFETs in the peripheral circuit area A
2
.
After removing the above patterned photoresist film, using another patterned photoresist film (not shown) covering the memory cell area A
1
and the active regions for the n-channel MOSFETs thus formed, the sidewall spacers
106
and the gate electrodes
104
as a mask, the remaining active regions of the substrate
101
in the peripheral circuit area A
2
are selectively ion-implanted with boron difluoride (BF
2
) with a dose of approximately 3×10
15
atoms/cm
2
, thereby forming p-channel MOSFETs (not shown) in the peripheral circuit area A
2
.
Following this, a Boron-doped Phosphor-Silicate Glass (BPSG) layer
109
with a thickness of approximately 400 nm is formed by a CVD process over the entire substrate
101
. The BPSG layer
109
serves as a first interlayer insulating layer located between the gate electrodes
104
and bit lines
108
which will be formed in the next step. The state at this stage is shown in FIG.
1
A.
Further, as shown in
FIG. 1B
, the first interlayer insulating layer
109
is selectively etched to form a contact hole
110
vertically extending to the corresponding one of the n
−
-type diffusion regions
105
in the memory cell area A
1
. A patterned conductive layer
108
serving as the bit lines is then formed on the first interlayer insulating layer
109
. The bit line
108
thus formed are contacted with and electrically connected to the corresponding one of the n
−
-type diffusion regions
105
in the memory cell area A
1
through the contact hole
110
.
Subsequently, a BPSG layer
111
serving as a second interlayer insulating layer is formed to cover the entire substrate
101
by a CVD process. The second interlayer insulating layer
111
and the underlying first interlayer insulating layer
109
are selectively etched to form conta

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