Semiconductor memory device with a reduce access time by...

Details Semiconductor memory device with a reduce access time by... Semiconductor memory device with a reduce access time by...

1999-04-22

2001-01-30

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S194000, C365S063000, C365S230080

Reexamination Certificate

active

06181631

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a semiconductor memory device for storing data in a computer and etc.
BACKGROUND OF THE INVENTION
The outline of a typical structure of a conventional semiconductor memory device is that four memory cell arrays are formed near four corners of a rectangular shaped semiconductor chip and a Y address buffer for outputting address data is formed on a nearly central portion thereof. Each memory cell array is combined with a Y address decoder, which selects a memory cell in the memory cell array and reads data stored therein in accordance with the Y address data, and a data amplifier, which amplifies the data read by the Y address decoder and outputs it to an output circuit for supplying the amplified data to an external circuit. Since the output circuit is situated on a side end of the semiconductor chip, the length of a wiring between the output circuit and the memory cell array situated on the right side of the semiconductor chip is inevitably different from that between the output circuit and the memory cell array situated on the left side. Accordingly, there arises a difference in a delay time of the data between those started from the memory cell arrays situated on the right and left sides of the semiconductor chip. In other words, an access time to the memory cell array on the right side is different from that to the same on the left side, and it is extremely desirable to remove this disadvantage.
SUMMARY OF THE INVENTION
The invention is made on the basis of the aforementioned background, and it is an object of the invention to provide a semiconductor memory device having a reduced access time by devising the layout of the circuit without elaborate modification.
According to the feature of the invention, and semiconductor device comprises:
plural memory cell arrays,
an address buffers for outputting address data,
address decoders, which are respectively combined with the plural memory cell arrays, select memory cells in the memory cell array in accordance with the address data and read data stored therein,
amplifiers, which respectively amplify the data and output amplified results as output data,
activation circuits, which respectively output activation signals for activating the amplifiers, and
an output circuit for outputting the output data to an external circuit,
wherein the plural memory cell arrays, the address buffer, the address decoders, the amplifiers, the activation circuits and the output circuit are respectively formed on a same semiconductor chip; and a length of a wiring between the address decoder combined with the memory cell array remote from the output circuit and the address buffer is shorter than that between the address decoder combined with the memory cell array near the output circuit and the address buffer.


REFERENCES:
patent: 5369619 (1994-11-01), Ohba
patent: 5699289 (1997-12-01), Talenaka
patent: 5943285 (1999-08-01), Kohno

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