Semiconductor memory device with a plurality of memory cells con

Details Semiconductor memory device with a plurality of memory cells con Semiconductor memory device with a plurality of memory cells con

1996-07-03

1998-03-31

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular connection

36518522, 36518524, G11C 1600

Patent

active

057346127

ABSTRACT:
When the upper limit value of a leakage current allowed by a read.detection/write circuit connected to a plurality of bit lines to read and write data from and in memory cells is represented by IL, Vs satisfies ##EQU1## (ln is the natural logarithm) where Vgh is the potential of a non-selected word line, Vta is the average threshold voltage of the memory cells, e is the standard deviation, s is the subthreshold coefficient, Vd is the potential of the bit lines, and Vs is the potential of a source line.

REFERENCES:
patent: 5355330 (1994-10-01), Hisamoto et al.
patent: 5596525 (1997-01-01), Iwahashi

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