Semiconductor memory device with a decoding peripheral circuit f

Details Semiconductor memory device with a decoding peripheral circuit f Semiconductor memory device with a decoding peripheral circuit f

1995-09-07

1997-06-17

Popek, Joseph A.

Static information storage and retrieval

Addressing

Counting

365200, 36523006, 365233, G11C 700

Patent

active

056403658

ABSTRACT:
A data register that stores the data corresponding to the selected memory cell in a memory cell array is provided near the memory cell array. A decoder that selects the data from the data register starts decoding in response to an address signal accessing the memory cells in synchronization with a clock signal determining the operation period. In the first half of an operation period of the clock signal, the decoder outputs a signal in response to a signal corresponding to the address signal determined in the preceding operation period. According to the output of the decoder, the data register is selected. In the latter half of the operation period, a signal corresponding to a new address signal for the next operation period is transferred to the decoder. By doing this, the output control signal in the decoder is caused to synchronize with a signal driving an address signal, enabling the proper address to be selected without fail.

REFERENCES:
patent: 4556975 (1985-12-01), Smith et al.
patent: 4951253 (1990-08-01), Sahara et al.
1995 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 130-131, K. Imamiya et al., "A 35ns-Cycle-Time 3.3V-Only 32Mb NAND Flash EEPROM".

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