Semiconductor memory device with a countermeasure to a...

Details Semiconductor memory device with a countermeasure to a... Semiconductor memory device with a countermeasure to a...

2002-06-17

2004-03-23

Tran, M. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S196000

Reexamination Certificate

active

06711044

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a countermeasure to a signal delay in such a device.
Japanese Laid-Open Patent Publication No. 10-178110 and Japanese Laid-Open Patent Publication No. 9-270468 each disclose a layout of a 6-transistor SRAM memory cell (i.e., a memory cell of an SRAM device including six transistors). Specifically, each of these publications discloses a method for reducing the aspect ratio (defined herein as the ratio of the dimension in the row direction in which word lines extend with respect to the dimension in the column direction in which bit lines extend) of a 6-transistor SRAM memory cell as illustrated in
FIG. 11A
, i.e., a method for laying out the components of the memory cell so that the dimension of the memory cell in the row direction in which word lines extend is greater than that in the column direction in which bit lines extend.
Specifically, each of these publications discloses a layout in which P-wells
102
a
and
102
b
are arranged on opposite sides of an N-well
101
so as to interpose the N-well
101
therebetween, as illustrated in FIG.
11
B. In this layout, six transistors (MN
0
, MN
1
, MN
2
, MN
3
, MP
0
and MP
1
) are arranged substantially in point symmetry with respect to a central point P
100
of the memory cell.
In the layout of a memory cell
1000
illustrated in FIG.
11
A and
FIG. 11B
, bit lines BL and BL are arranged on the P-well
102
a
and the P-well
102
b
, respectively. The drive transistors MN
0
and MN
1
, which are NMOS transistors, are laid out substantially in point symmetry with respect to the central point P
100
of the memory cell
1000
as described above, and are arranged over the P-well
102
a
and the P-well
102
b
, respectively. The access transistors MN
2
and MN
3
, which are NMOS transistors, are also laid out substantially in point symmetry with respect to the central point P
100
of the memory cell
1000
as described above, and are arranged over the P-well
102
a
and the P-well
102
b
, respectively. Moreover, the load transistors MP
0
and MP
1
, which are PMOS transistors, are also laid out substantially in point symmetry with respect to the central point P
100
of the memory cell
1000
, and are both arranged over the N-well
101
. The load transistors MP
0
and MP
1
extend in two lines parallel to each other in the direction in which bit lines extend, whereby the width of the PMOS region (the width of the N-well
101
) is increased accordingly.
FIG. 12A
is a top view schematically illustrating a structure of an SRAM device in which the memory cells
1000
illustrated in FIG.
11
A and
FIG. 11B
are arranged in a matrix pattern, and
FIG. 12B
is a cross-sectional view illustrating a bit line provided along line X—X shown in FIG.
12
A.
FIG. 13A
is a top view schematically illustrating a structure of another SRAM device in which high-aspect-ratio memory cells (longitudinal-type cells) are arranged in a matrix pattern, and
FIG. 13B
is a cross-sectional view illustrating a bit line provided along line Y—Y shown in FIG.
13
A.
Assuming that the memory cells illustrated in FIG.
12
A and
FIG. 13A
are made with the same design rule, the SRAM device illustrated in
FIG. 12A
, which uses the memory cells
1000
, has a smaller dimension in the column direction in which bit lines extend, as compared to the SRAM device illustrated in
FIG. 13A
, which uses the longitudinal-type cells. Thus, as can be seen from a comparison between FIG.
12
A and
FIG. 13A
, the length of the bit line can be reduced in the SRAM device illustrated in
FIG. 12A
, which uses the memory cells
1000
, as compared to the SRAM device illustrated in
FIG. 13A
, which uses the longitudinal-type cells. In practice, the length of the bit line of the SRAM device illustrated in
FIG. 12A
, which uses the memory cells
1000
, is about ⅓ of that of the bit line of the SRAM device illustrated in
FIG. 13A
, which uses the longitudinal-type cells.
Each bit line provided in a semiconductor memory device includes a portion (“extended portion”) that extends in the column direction of the matrix pattern in which a plurality of memory cells are arranged, and another portion (“contact plug”) that is connected to an access transistor of each memory cell. Therefore, if the number of contact plugs increase along with an increase in the degree of integration of memory cells, the capacitance of the contact plugs increases, thereby increasing the total line capacitance of the bit line. For example, in SRAM devices, highly-integrated mask ROM device, etc., using memory cells having a small ratio of the dimension in the direction in which word lines extend with respect to the dimension in the direction in which bit lines extend (longitudinal-type cells), the proportion of the contact plug capacitance with respect to the total line capacitance of the bit line is particularly large, and thus the bit line delay is substantial.
However, with the conventional method as described above, the length of a contact plug between a transistor and the extended portion of a bit line cannot be changed. Therefore, it is not very effective in reducing the total line capacitance of a bit line. In other words, it is not very effective in reducing the bit line delay. This will now be described in detail.
Typically, the length of a contact plug running through one wiring layer is 1300 nm, and the total length of a contact plug running through three wiring layers is 3900 nm. In the SRAM device illustrated in
FIG. 13A
, which uses longitudinal-type cells, the length of the extended portion of a bit line per two memory cells (the dimension in the column direction of the memory cells) is about 1700 nm. In a case where one bit line includes one contact plug per two memory cells, the total of the length of the extended portion of the bit line per two memory cells and the length of the contact plug is 5600 nm (1700 nm+3900 nm).
Using the memory cell
1000
illustrated in
FIG. 12A
, if the length of a bit line is reduced to ⅓, the total of the length of the bit line and the length of the contact plug will be about 4460 nm. Since the length of the contact plug does not change, the total of the length of the extended portion of the bit line and the length of the contact plug is reduced only by about 20%. Thus, the total line capacitance of the bit line is reduced only by about 20%.
SUMMARY OF THE INVENTION
The present invention, which has been made to solve the problem as described above, has an object to reduce a signal delay in a semiconductor memory device.
A semiconductor memory device of the present invention includes: a substrate; a plurality of memory cells arranged in a matrix pattern on a primary surface of the substrate; a sense amplifier provided in each column for detecting data of the memory cells that are arranged along the column; a plurality of wiring layers formed on the substrate; and a plurality of data lines provided in each column and connected to the memory cells that are arranged in the column, wherein the data lines are connected commonly to the sense amplifier but via different paths, and a data line having a longer path length is provided by using a wiring layer that is on a higher level.
With the present invention, the number of memory cells connected to one data line is reduced. Therefore, the number of contact plugs for connecting memory cells and one data line is reduced. Thus, the total line capacitance of each data line including the contact plugs is reduced. Since the line capacitance is in proportion to the signal delay along the line, the signal delay along one data line is reduced by the reduction in the total line capacitance of the data line including the contact plugs.
It is preferred that: the plurality of data lines each include contact plugs for connection to the plurality of memory cells that are arranged in one column; and a total line capacitance of each data line including the contact plugs is substantially equal to those of

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