Semiconductor memory device which prevents destruction of data

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S185240, C365S002000, C714S773000

Reexamination Certificate

active

11498142

ABSTRACT:
A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the n-valued data by a first write operation and a second write operation. A read section sets a potential of a word line, and reads data from a memory cell in the memory cell array. If data read by the read section and written in the second write operation includes an uncorrectable error, a control section changes a potential of a word line supplied to the read section when reading data written in the first write operation.

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