Semiconductor memory device utilizing two data line pairs and re

Details Semiconductor memory device utilizing two data line pairs and re Semiconductor memory device utilizing two data line pairs and re

1996-06-20

1997-07-22

Zarabian, Amir

Static information storage and retrieval

Addressing

Counting

365203, G11C 800

Patent

active

056509804

ABSTRACT:
One of the two data input/output line pairs and the selected bit line pair included in a memory cell array are connected by a column switch, and the read out data is output to a preamplifier through a switching circuit. A data input/output line pair of the data input/output line pairs which is not used for data transmission is equalized by an equalizing circuit. Therefore, data readout and equalizing operation are carried out in parallel, thereby achieving high-speed data readout.

REFERENCES:
patent: 4941128 (1990-07-01), Wada
patent: 5416743 (1995-05-01), Allan

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