Static information storage and retrieval – Addressing
Patent
1983-12-28
1986-10-14
Moffitt, James W.
Static information storage and retrieval
Addressing
365179, 307449, G11C 800, G11C 1136
Patent
active
046176535
ABSTRACT:
A semiconductor memory device includes a plurality of memory cells arranged in a matrix form and a decoder circuit selecting a row of the matrix in response to an address signal. The decoder circuit includes a first-stage decoder having a plurality of first-stage decoding elements and a second-stage decoder having a plurality of second-stage decoding elements. Each first-stage decoding element is connected to a plurality of second-stage decoding elements. Each of the first-stage decoding elements receives predetermined higher bits of the address signals. One of the first-stage decoding elements is selected upon one access command. Each of the plurality of second-stage decoding elements receives the address signals. One of the rows of the matrix is selected in response to the the address signals when the corresponding first-stage decoding element operates, whereby the power consumption is reduced.
REFERENCES:
patent: 4369503 (1983-01-01), Isogai
patent: 4385370 (1983-05-01), Isogai
Fukushima Toshitaka
Matsuzaki Yasuro
Ueno Kouji
Fujitsu Limited
Gossage Glenn A.
Moffitt James W.
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