Semiconductor memory device using tapered arrangement of...

Details Semiconductor memory device using tapered arrangement of... Semiconductor memory device using tapered arrangement of...

2006-09-12

2006-09-12

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S230030

Reexamination Certificate

active

07106612

ABSTRACT:
A semiconductor memory device optimizes current consumption by using proper sub-bank arrangement and at least two different kinds of LIO sense amplifiers having different driving capabilities. The driving capabilities of the LIO sense amplifiers are controlled in a tapered manner depending on whether a corresponding sub-bank of the LIO sense amplifier is arranged nearer to, or farther away from, its corresponding GIO sense amplifier. In other words, the farther that a sub-bank of an LIO sense amplifier is away from its corresponding GIO sense amplifier, the greater its driving capability.

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