Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Utility Patent
1997-10-07
2001-01-02
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S149000, C365S230030
Utility Patent
active
06169701
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and relates to a novel drive of a bit line transfer gate for bit line pair selection in a shared sense amplifier system in which bit line pairs on both sides use a common sense amplifier.
2. Description of the Related Art
In dynamic random access memories (DRAMs) larger capacity, lower power source voltage and lower power consumption are being demanded. The power source voltage Vcc is lowered from the conventional 5V to 3V and the power source voltage Vcc within the chip is boosted to generate a boosted power source voltage Vpp of for example 5V.
Also, in order to respond to the demands for increasing capacity, a shared sense amplifier system is employed in which a sense amplifier array is arranged between two memory cell arrays and the sense amplifiers are shared by respective bit line pairs of respective memory cell arrays. With such a shared sense amplifier system, thanks to sharing of the sense amplifier array, their number can be reduced. However, for this purpose it is necessary to provide bit line transfer gates for selection of either side of bit line pairs between the bit line pairs and sense amplifiers in order to effect connection and isolation of these, the bit line pairs of the selected memory cell array being connected to the sense amplifiers while the bit line pairs of the non-selected memory cell array are isolated from the sense amplifiers.
To achieve this, there is provided a bit line transfer gate drive circuit that, during the pre-charging period, allows the bit line transfer gates on both sides to conduct and, during the active period, makes the bit-line transfer gates on the non-selected side non-conductive, while conduction of the bit-line transfer gates on the selected side is maintained. Specifically, this bit line transfer gate drive circuit, during pre-charging, makes the potential of the gate electrodes of the bit line transfer gates H level, higher than the internal power source, and, in the active period, lowers the potential of the gate electrodes on the non-selected side to L level, while maintaining that of those on the selected side at H level.
In a DRAM, the potential of a bit line connected to a memory cell is changed depending on the charge storage condition of the capacitor for charge storage provided in the memory cell, and this minute change of potential is detected by a sense amplifier. Thus, since a DRAM is a destructive read device, once this potential difference of the bit line pair has been detected by the sense amplifier and amplified, this potential must again be rewritten to the memory cell capacity through the bit line.
With increase in capacity of DRAMs in recent years, memory cell capacities have become very small, so during rewriting it is necessary to drive the potential of the H-level bit line to quite a high level. For this purpose, when rewriting during the active period, it is necessary to pull up the potential of the gate electrode of the bit line transfer gates referred to above to a higher potential than the high potential applied to the bit line. For example, if the H-level bit line potential is the power source voltage Vcc level, it is necessary to pull the gate potential of the bit line transfer gate up to a boosted power source Vpp level higher than power source voltage Vcc.
However, generation of boosted power source Vpp within the chip is a factor that increases power consumption. In particular, in a drive circuit for bit line transfer gates, the ability to drive the gate electrodes of the bit line transfer gates respectively provided between a large number of bit line pairs and sense amplifiers is demanded; thus the load capacity to be driven is large and very large power consumption is needed to drive the gates up to the boosted power source level mentioned above.
Such increased power consumption raises the chip temperature and is a considerable obstacle to increasing capacity and raising speed of operation.
An object of the present invention is therefore to provide a semiconductor memory device wherein the above problems are eliminated and the power consumption of the bit line transfer gate drive circuit is reduced.
A further object of the present invention is to provide a semiconductor memory device having a bit line transfer gate drive circuit that is operated by power source voltage without needing to use a boosted power source.
SUMMARY OF THE INVENTION
In order to achieve the above objects, in the present invention, the gate electrodes of the bit line transfer gates for bit line pair selection that perform connection and isolation of the sense amplifiers and bit line pairs are put into floating condition during activation of the sense amplifier in the active period. Thus, a system is adopted according to which the potential of the bit line is driven to power source voltage Vcc or a high voltage corresponding thereto by the sense amplifier in the active condition, the pre-charging potential of the bit line pair being made lower than half the power source voltage Vcc, for example ground potential Vss.
Thanks to the amplification action of the sense amplifier, by utilising the fact that one side of the plurality of bit line pairs is inevitably driven from low potential to the power source voltage Vcc level or high voltage corresponding thereto, the potential of the gate electrodes which are in floating condition is boosted higher due to capacitative coupling, enabling the potential of the bit line on rewriting to be boosted to a voltage driven by the sense amplifier, for example power source voltage.
Specifically, according to this invention there are provided: semiconductor memory device comprising: first and second memory cell arrays comprising a plurality of word lines, a plurality of bit line pairs intersecting thereto, and memory cells provided at intersections therebetween; a pre-charging circuit that drives the bit lines pairs together to a first potential in a pre-charging period; a row of sense amplifiers, arranged between the first and second memory cell arrays, in an active period, detecting the potential differences of these bit lines pairs and driving one of these bit lines to a second potential higher than the first potential; first bit line transfer gates for selection of the bit line pairs, respectively arranged between the bit line pairs of the first memory cell array and the sense amplifiers, conducting when the first memory cell array is selected; second bit line transfer gates for selection of the bit line pairs, respectively arranged between the bit line pairs of the second memory cell array and the sense amplifiers, conducting when the second memory cell array is selected; and a bit line transfer gate drive circuit which puts the gate electrodes of the first or second bit line transfer gates into floating condition when, in the active period, the corresponding memory cell array is selected.
With such a construction, the bit line transfer gate drive circuit can make the gate electrodes be self-boosted by the drive operation of the sense amplifier simply by putting them in floating condition from the power source voltage Vcc or high level corresponding thereto, without needing to drive the gate electrodes of the bit line transfer gates to a boosted power source Vpp higher than the H level of the bit line. Power consumption can therefore be greatly reduced.
REFERENCES:
patent: 5243574 (1993-09-01), Ikeda
patent: 5740113 (1998-04-01), Kaneko
Eto Satoshi
Kanou Hideki
Matsumiya Masato
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Ho Hoai V.
Nelms David
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