Semiconductor memory device using open data line arrangement

Details Semiconductor memory device using open data line arrangement Semiconductor memory device using open data line arrangement

2000-11-29

2002-06-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S069000, C257S776000

Reexamination Certificate

active

06400596

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and particularly relates to structures of memory array and sense amplifier units included in the semiconductor device.
BACKGROUND OF THE INVENTION
A list of references referred to by the present specification is as follows. Reference will be made to such references according to reference numbers. They are [Reference 1]: Japanese Patent Laid-Open No. H5-41081, [Reference 2]: Ultra Micro-Fabrication Technology, pp. 27-41, Edited by The Japan Society of Applied Physics/Author: Gi Tokuyama, First Edition issued by ohm Co., Ltd., Feb.25, 1997, and [Reference 3]:Japanese Patent Laid-Open No. H9-135004.
The [Reference 1] describes the layout or placement of sense amplifiers and data lines where an open data line arrangement is taken in divided plural memory mats. In particular,
FIG. 3
describes sense amplifiers of a so-called alternate-layout type that one sense amplifier is placed per two data lines adjacent to each other, and one thereof is connected to its corresponding sense amplifier of the right side sense amplifier block, whereas the remaining one is connected to its corresponding sense amplifier of the left side sense amplifier block. [Reference 2] describes a phase shift method indicating one lithography technology for forming micro or fine patterns on the semiconductor wafer. [Reference 3] describes an example illustration of mask patterns in a memory array of a so-called one intersecting-point memory cell system.
Two types of typical memory array constituting methods of (1) the one intersecting-point memory cell method or system (or open data line arrangement) and (2) the two intersecting-point memory cell method or system (folded data line arrangement) are known for a dynamic random access memory (DRAM). Commercializing of products has been started from DRAM of the one intersecting-point memory cell system historically. However, the one intersecting-point memory cell system has been changed over to the two intersecting-point memory cell system with a 64K-bit DRAM as the boundary. The present commercialized 256M-bit DRAM also uses the two intersecting-point memory cell system. It is however known that the theoretical minimum memory cell area employed in DRAM is equal to eight times (8F
2
) the square of the minimum feature size F in the two intersecting-point memory cell system, whereas the minimum memory cell area is equal to 6F
2
reduced by 25% from 8F
2
in the one intersecting-point memory cell system. Here, the minimum feature size F corresponds to the minimum interval required to separate between patterns, which is determined by the technology of processing a semiconductor integrated circuit, such as optical lithography or the like. The minimum feature size F is the design unit. Namely, all the mask patterns are designed with F as the unit in the semiconductor integrated circuit, and a specific size of F is applied thereto according to a realistic processing technology. If the two intersecting-point memory cell system is kept using from now on, then one simply depends on a reduction in the minimum feature size F. A drastic reduction in memory cell area cannot be expected. Therefore, the inventors of the present invention have discussed the application of the one intersecting-point memory cell system capable of expecting the reduction in the memory cell area under the design technique to an array configuration or structure of mass-storage memories.
FIG. 23
shows a memory array which adopts bit-line multi-division and a sense-amplifier alternate layout in the one intersecting-point memory cell system described in
FIG. 3
of [Reference 1]. In the present memory array, the connections of sense amplifiers and data lines are made according to a simple one rule. Data lines for one memory array (e.g., SMA(i)) are connected to an adjacent two sense amplifiers (e.g., SA
1
and SA
2
) on alternate lines (e.g., DR(i)
1
and DR(i)
2
). As shown in this figure, one intersecting-point array having memory cells at all points where word lines and data lines intersect, needs to lay out one sense amplifier for two data lines even if the sense amplifiers are alternately placed. The pitch of wiring for implementing the layout shown in
FIG. 23
is limited by the lithography technology.
As the lithography technology for forming fine- or micro-patterns, the phase shift method has been used in recent years. Traditional photo-masks had openings for controlling the simple transmission of light alone. On the other hand, each of photo-masks employed in the phase shift method has a first opening for allowing light to pass therethrough, and a second opening for allowing the light to pass therethrough with the phase of the transmitted light as a 180° difference with respect to the first opening (shifting the phase thereof by 180° and allowing the light to pass). When lights cancel each other out in an area to which the first opening and the second opening adjoin, finer lithography is accomplished even if the same wavelength of light is used. Details on the phase shift method itself have been described in [Reference 2]. The assignment of phases to their corresponding patters (phase layout or arrangement) becomes an important upon adoption of the phase shift method. Namely, the wiring-to-wiring pitch must be extended depending on phase assignment methods. Unless the most suitable phase assignment is done, a layout area cannot be reduced.
The inventors of the present invention have noticed the need for special consideration to the method of connecting the sense amplifiers and the data lines for the memory cell arrays upon forming the memory arrays having adopted the bit line multi-division and the sense amplifier alternate layout in the one intersecting-point memory cell system by using the phase shift method. Namely, unless consideration is given to the phase assignment, wiring pitch and patterns, failures such as a break in wiring and a short circuit in wiring are apt to occur in the boundary between areas in which patterns such as those for the memory arrays and sense amplifiers are different.
SUMMARY OF THE INVENTION
An object of the present invention is therefore to provide a system for laying out sense amplifiers, which is required to implement a one intersecting-point system corresponding to a memory array configuration or structure capable of reducing a chip area.
More specifically, the present invention aims to implement a pattern system for wiring data lines between memory arrays and sense amplifiers, which is suitable for lithography using a phase shift method.
A typical example of the present invention will be explained as follows: There is provided a semiconductor device comprising a first memory array including a plurality of first memory cells provided at points where a first data line group including first through fourth data lines, and a plurality of first word lines intersect; a second memory array including a plurality of second memory cells provided at points where a second data line group including fifth through eighth data lines, and a plurality of second word lines intersect; and a first sense amplifier block provided in an area between the first and second memory arrays and including first and second sense amplifiers adjacent to each other, wherein the first sense amplifier is connected to the first data line and one of the data lines included in the second data line group so as to take an open data line arrangement, the second sense amplifier is connected to the fourth data line and another one of the data lines included in the second data line group so as to take an open data line arrangement, and the second and third data lines are placed between the first data line and the fourth data line.


REFERENCES:
patent: 5396450 (1995-03-01), Takashima et al.
patent: 5691933 (1997-11-01), Takenaka
patent: 5838038 (1998-11-01), Takashima et al.
patent: 6043562 (2000-03-01), Keeth
patent: 6222275 (2001-04-01), Keeth
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