Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2006-08-01
2006-08-01
Le, Thong Quoc (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S185230
Reexamination Certificate
active
07085162
ABSTRACT:
A semiconductor memory device has a memory cell array and a row decoder circuit configured to select a word line in the memory cell array. The row decoder circuit includes a first transistor of a first conductivity type and a second transistor of a second conductivity type. A source or a drain of the first transistor is connected to a corresponding one of word lines. The first transistor applies a voltage to the word line and a source or a drain of the second transistor is connected to a gate of the first transistor. When the word line in a selected block is biased to a first voltage which is higher than a power supply voltage, the second transistor applies a second voltage to the gate of the first transistor, and the second voltage is higher than the power supply voltage.
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Imamiya Kenichi
Nakamura Hiroshi
Banner & Witcoff , Ltd.
Le Thong Quoc
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