Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2005-06-28
2005-06-28
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185230
Reexamination Certificate
active
06912157
ABSTRACT:
A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The decoder circuit includes a plurality of first transistors of a first conductivity type in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.
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Imamiya Kenichi
Nakamura Hiroshi
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Le Thong Q.
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