Semiconductor memory device using only single-channel...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185230

Reexamination Certificate

active

06912157

ABSTRACT:
A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The decoder circuit includes a plurality of first transistors of a first conductivity type in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.

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patent: 5555204 (1996-09-01), Endoh et al.
patent: 5706241 (1998-01-01), Nakamura
patent: 6249467 (2001-06-01), Pereira et al.
patent: 6353242 (2002-03-01), Watanabe et al.
patent: 6512253 (2003-01-01), Watanabe et al.
patent: 2003/0107055 (2003-06-01), Watanabe et al.

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