Semiconductor memory device using magneto resistive element...

Details Semiconductor memory device using magneto resistive element... Semiconductor memory device using magneto resistive element...

2002-04-19

2003-11-25

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Magnetic field

C257S424000, C257S427000, C365S158000, C365S171000, C365S173000

Reexamination Certificate

active

06653703

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-122883, filed Apr. 20, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly, to a magnetic memory apparatus (MRAM: Magnetic Random Access Memory) using a tunneling magneto resistive (TMR) element as a memory element and a method of manufacturing the same.
2. Description of the Related Art
In recent years, a magnetic random access memory (MRAM) utilizing the tunneling magneto resistive effect has been proposed as an information memory element.
FIG. 57
is an oblique view schematically showing a conventional semiconductor memory device. The construction of the MRAM will now be described briefly with reference to FIG.
57
.
As shown in
FIG. 57
, a plurality of bit lines
23
and a plurality of write word lines
13
are arranged to cross each other at right angles so as to form a matrix configuration, and a TMR element
24
is arranged at each intersection between the bit line
23
and the write word line
13
. The TMR element
24
is connected to the bit line
23
through an upper electrode (not shown) and is also connected to a switching element (MOSFET)
5
through a lower electrode
17
. The gate electrode of the MOSFET acts as a read word line
3
.
The TMR element
24
comprises a magnetically fixed layer
18
connected to the lower electrode
17
, a magnetic recording layer
20
connected to the bit line
23
through upper electrode, and a tunnel barrier layer (tunnel junction film)
19
interposed between the magnetically fixed layer
18
and the magnetic recording layer
20
.
The magnetically fixed layer
18
has a direction of magnetization fixed to an easy axis direction (EA direction). On the other hand, the magnetic recording layer
20
has two magnetization directions determined by the mutual function between the magnetic recording layer
20
and the magnetically fixed layer
18
, said two magnetization directions corresponding to the information memory states of “1” and “0”. The resistance of the tunnel junction is rendered lowest when the direction of magnetization of the magnetic recording layer
20
is made equal to the magnetization direction of the magnetically fixed layer
18
, and is rendered highest when the direction of magnetization of the magnetic recording layer
20
is made opposite to that of the magnetically fixed layer
18
. The particular change in the resistance is read by allowing an electric current to flow through the TMR element
24
so as to make it possible to judge the information memory states of “1” and “0”.
The MRAM memory cell of the particular construction is designed such that the magnetization direction of only the magnetic recording layer
20
is reversed by the magnetic field synthesized by the current magnetic field generated from the current flowing through both the selected bit line
23
and the selected write word line
13
, though the magnetization direction of the magnetically fixed layer
18
remains unchanged. Therefore, where data is written in an optional cell, the magnetization direction of the magnetic recording layer
20
is reversed as described above so as to write information in the selected cell. On the other hand, where data is read from an optional cell, the bit line
23
and the read word line
13
are selected and a current value flowing from the bit line
23
through the TMR element
24
, the lower electrode
17
, and the switching MOSFET
5
is compared with, for example, a reference cell so as to judge the information memory states of “1” and “0” denoting the resistance state of the cell.
FIG. 58
shows by arrows the state of magnetization of the magnetic recording layer included in the conventional semiconductor memory device. As shown in
FIG. 58
, domains
100
in which the magnetization vectors in the longitudinal direction are turned are actually formed in both edge portions of the magnetic recording layer
20
, though it is ideal for all the magnetization directions
28
to be aligned in the easy axis direction (EA direction) in the magnetic recording layer
20
. A so-called “diamagnetic field” is generated by the presence of these domains
100
. As a result, in the region in which the diamagnetic field has been generated, it is impossible to maintain uniform the original tunnel resistance corresponding to the information memory states of “1” and “0”. This gives rise to the problem that the S/N ratio of the signals of “1” and “0” that can be output is degraded, resulting in failure to ensure a sufficient operating margin and to read out data.
In order to overcome the above-noted problem, the length in the longitudinal direction of the cell is increased in the prior art so as to achieve a vertical-longitudinal ratio of, for example, at least 3, thereby ensuring an area required for the reading of data even if a diamagnetic field is generated in each of the both edges of the cell. However, the measure pointed out above leads to enlargement of the cell area so as to provide a large obstacle to the miniaturization of the MRAM cells in the future.
As described above, the prior art is defective in that the domains
100
generated in the cell degrade the operating margin in reading the data and make it difficult to miniaturize the cell.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor memory device, comprising a first wiring extending in a first direction, a second wiring extending in a second direction differing from the first direction, and a magneto resistive element arranged between the first wiring and the second wiring and comprising a first portion and a second portion, the second portion being in contact with the second wiring and extending along the second wiring to reach an outside region positioned outside the first portion.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device provided with a magneto resistive element including a first portion and a second portion, comprising extending the second portion along a second wiring to reach an outside region positioned outside the first portion by patterning the second portion together with the second wiring.


REFERENCES:
patent: 5640343 (1997-06-01), Gallagher et al.
patent: 5946227 (1999-08-01), Naji
patent: 5946228 (1999-08-01), Abraham et al.
patent: 5982658 (1999-11-01), Berg et al.
patent: 6509621 (2003-01-01), Nakao
patent: 0 936 624 (1999-08-01), None
patent: 1 085 586 (2001-03-01), None
patent: 2000-195250 (2000-07-01), None

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