Semiconductor memory device using a relatively low-speed...

Details Semiconductor memory device using a relatively low-speed... Semiconductor memory device using a relatively low-speed...

1999-11-19

2001-02-20

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230010, C365S238500

Reexamination Certificate

active

06192003

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor memory devices and, more particularly, to a DRAM-type semiconductor memory device using a relatively low-speed clock frequency and capable of latching a row address and a column address with one clock signal and performing a page operation.
First, a dynamic RAM (DRAM) device as a conventional semiconductor memory device will be described with reference to the drawings.
FIGS.
5
(
a
) and
5
(
b
) are timing charts for the data I/O of the conventional DRAM, of which FIG.
5
(
a
) shows a read operation and FIG.
5
(
b
) shows a write operation. In a read operation, as shown in FIG.
5
(
a
), a row address strobe (/RAS) signal, which is a first clock signal, is initially caused to fall to activate a row-related circuit that has been in a precharged state so far, whereby a memory operation is initiated and the row address is latched. After a lapse of a given time, a column address strobe (/CAS) signal, which is a second clock signal, is subsequently caused to fall, whereby a read operation is initiated and a column address is latched. This activates memory cells connected to a selected word line as well as a sense amplifier circuit connected to a selected pair of bit lines. At this time, a write control signal /WE is brought to the HIGH level to disable a write operation, whereby a potential difference read onto the pair of bit lines connected to a selected memory cell is amplified to determine valid data and further output to the outside via a read amplifier or the like.
In a write operation also, as shown in FIG.
5
(
b
), the /RAS signal is initially caused to fall to latch a row address and then the /CAS signal is caused to fall to latch a column address. This activates the memory cell connected to the selected word line as well as a sense amplifier connected to the selected pair of bit lines. At this time, the write control signal /WE is shifted the LOW level to enable a write operation and valid data to be held in the selected memory cell is input from a write amplifier or the like.
In the present embodiment, the mark / preceding the name of a signal indicates that the signal is inverted. The signal preceded by the mark / is in the active state when it is LOW (active LOW).
However, the conventional DRAM device requires two clock signals for synchronization to latch a row address and a column address for selecting one from a plurality of memory cells in a memory cell array, which are the RAS signal and the CAS signal. Accordingly, control operation over the clockbecomes complicated. In the case of merging the DRAM and a logic circuit into one chip, designing difficulties are particularly increased.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to solve the conventional problem and provide easy handling of a clock signal for the synchronization of a semiconductor memory.
To attain the object, the present invention has allotted a trigger used to latch the row and column addresses of an address signal to the both edges of one clock signal.
Specifically, a semiconductor memory device according to the present invention comprises: a memory cell array having a plurality of memory cells each for retaining data; a plurality of word lines selectively activated by a row address signal from the outside; a plurality of bit lines each being selected by a column address signal from the outside; sense amplifiers each for amplifying data read onto the bit lines connected thereto; row address latch means for latching the row address signal by using, as a trigger, a first edge of a clock signal from the outside; sense amplifier activating means for activating the sense amplifiers after a lapse of a given delay time from the first edge; column address latch means for latching the column address signal by using, as a trigger, a second edge of the clock signal occurring after the first edge; and precharge signal generating means for generating a precharge signal for precharging the bit lines after a lapse of a given delay time from the second edge.
In the semiconductor memory device of the present invention, the row address is latched by using either the rising edge or falling edge of one clock signal and the sense amplifier is activated after a lapse of a given time from the latching of the row address, while the column address is latched by using the other edge and the bit lines are precharged after a lapse of a given time from the latching of the column address. As a result, a selective read or write operation with respect to the plurality of memory cells can be performed periodically and positively by using one clock. This achieves easy handling of a clock signal for synchronizing a memory operation.
In the semiconductor memory device of the present invention, the first and second edges of the clock signal preferably correspond to a falling edge and a rising edge, respectively, or to a rising edge and a falling edge, respectively. This implements a high-speed operation in which a latency, which is the time required to execute one instruction, is 1 clock.
Preferably, the semiconductor memory device of the present invention further comprises write control means for judging whether a write control signal for determining whether data should be written in the memory cell or not is in one state or in the other state by using the second edge as a trigger and enabling a write operation when the result of judgment indicates the one state or disabling the write operation when the result of judgment indicates the other state. This ensures that either the write operation or read operation is solely performed.
Preferably, the semiconductor memory device of the present invention further comprises page-mode control means for judging whether a page-mode control signal for determining whether a page mode should be set or not is in one state or in the other state by using, as a trigger, the first or second edge of the clock signal and enabling the precharging of the bit lines by using the second edge as a trigger, while enabling the operation of latching another row address signal by using a third edge occurring after the second edge as a trigger if the result of judgment indicates one state or disabling the precharging of the bit lines by using the second edge as a trigger, while disabling the operation of latching another row address signal by using the third edge as a trigger if the result of judgment indicates the other state. In the arrangement, if the result of judgment indicates one state such as the OFF state, the precharging of the bit lines on the second edge used as a trigger is enabled and the operation of latching another row address signal by using the third edge occurring after the second edge is enabled. Accordingly, the operational mode becomes a normal mode (non-page mode). If the result of judgment indicates the other state such as the ON state, on the other hand, the precharging of the bit lined on the second edge used as a trigger is disabled and the operation of latching another row address signal by using the third edge as a trigger is disabled. This prevents the destruction of data read into the sense amplifier in the clock cycle including the second edge and implements the page mode.
In this case, the first, second, and third edges of the clock signal preferably correspond to a falling edge in a first clock cycle, a rising edge in the first clock cycle, and a falling edge in a second clock cycle subsequent to the first clock cycle in this order or correspond to the rising edge in the first clock cycle, the falling edge in the first clock cycle, and the rising edge in the second clock cycle subsequent to the first clock cycle in this order. This implements a high-speed operation in which a latency, which is the time required to execute one instruction, is 1 clock.
Preferably, the semiconductor memory device of the present invention further comprises: a data output circuit for outputting data amplified by the sense amplifiers to the outside and data output disabling means for disabli

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