Static information storage and retrieval – Associative memories
Reexamination Certificate
2008-08-15
2010-11-02
Elms, Richard (Department: 2824)
Static information storage and retrieval
Associative memories
C365S049170, C365S200000, C365S203000
Reexamination Certificate
active
07826241
ABSTRACT:
A pre-decoded address is generated at a high speed in a semiconductor memory device. The device comprises a pre-decoder (210) for generating a first pre-decoded address (PDA1) by pre-decoding the input address (ADD), a CAM circuit (220) for activating the match signal (MT) by responding to the indication of a defective memory cell by the input address (ADD), a ROM circuit (230) for outputting a second pre-decoded address (PDA2) and an enable signal (ES) in response to the activation of the match signal (MT), and a multiplexer (240) for selecting either the first or second pre-decoded address (PDA1or PDA2) on the basis of the enable signal (ES). According to the present invention, there is no need to use a circuit with numerous stages as there is in substituted logic; accordingly, pre-decoded addresses can be generated at a high speed.
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Goel Ankur
Kumaran Sahadevan A.
Mishra Sanjay Kumar
Rengarajan Krishman S.
Elms Richard
Elpida Memory Inc.
McGinn IP Law Group PLLC
Nguyen Hien N
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