Semiconductor memory device that can relieve defective address

Static information storage and retrieval – Associative memories

Reexamination Certificate

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Details

C365S049170, C365S200000, C365S203000

Reexamination Certificate

active

07826241

ABSTRACT:
A pre-decoded address is generated at a high speed in a semiconductor memory device. The device comprises a pre-decoder (210) for generating a first pre-decoded address (PDA1) by pre-decoding the input address (ADD), a CAM circuit (220) for activating the match signal (MT) by responding to the indication of a defective memory cell by the input address (ADD), a ROM circuit (230) for outputting a second pre-decoded address (PDA2) and an enable signal (ES) in response to the activation of the match signal (MT), and a multiplexer (240) for selecting either the first or second pre-decoded address (PDA1or PDA2) on the basis of the enable signal (ES). According to the present invention, there is no need to use a circuit with numerous stages as there is in substituted logic; accordingly, pre-decoded addresses can be generated at a high speed.

REFERENCES:
patent: 5267213 (1993-11-01), Sung et al.
patent: 5930194 (1999-07-01), Yamagata et al.
patent: 6006313 (1999-12-01), Fukumoto
patent: 6614685 (2003-09-01), Wong
patent: 6895537 (2005-05-01), Kawagoe et al.
patent: 7525828 (2009-04-01), Yabe
patent: 2001/0056557 (2001-12-01), Kawagoe et al.
patent: 09-007390 (1997-10-01), None
patent: 2001-358296 (2001-12-01), None

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