Semiconductor memory device that can access two regions...

Details Semiconductor memory device that can access two regions... Semiconductor memory device that can access two regions...

2001-01-16

2002-03-19

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S189011, C365S189050, C365S230080

Reexamination Certificate

active

06359803

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device that can operate at high speed.
2. Description of the Background Art
Recent computers are incorporated with a main memory and a cache memory. A dynamic random access memory (DRAM) or the like is generally used for the main memory. The dynamic random access memory having a large capacity is slow in operation. Therefore, for the purpose of temporarily storing a portion of data of the main memory and carrying out frequent access to a particular address speedily, a cache memory capable of high speed operation, but of small storage capacity, is used. A static random access memory (SRAM) or the like is generally used for the cache memory.
There is the case where data of a large amount is read out, modified, and written back in a system incorporating such a cache memory. For example, such a process includes the image data correction process and the like.
FIG. 16
is a schematic diagram to describe the operation of reading out data, modifying the data, and writing back the data.
Referring to
FIG. 16
, a main memory
506
has addresses M
0
-M
13
, and a cache memory
504
has addresses C
0
-C
4
. Here, it is assumed that the amount of data that can be stored in one of addresses C
0
-C
4
of the cache memory
504
is equal to the amount of data that can be stored in one of addresses M
0
-M
13
of the main memory
506
.
The operation of sequentially reading out data stored in addresses M
0
-M
13
of the main memory
506
, modifying the data in a CPU
502
, and then writing back the data into addresses M
0
-M
13
of the main memory
506
will be described here.
At step S
1
, data stored in address M
0
of the main memory
506
is copied into address C
0
of the cache memory
504
, and then read into the CPU
502
. The CPU
502
outputs the modified data. In general, the modified data is temporarily stored in the cache memory
504
. When there is no more empty region in the cache memory
504
, the data in the cache memory
504
is transferred to the main memory
506
. At the current point, the modified data is stored in address C
0
of the cache memory
504
, and not yet transferred to the main memory
506
.
At steps S
2
-S
5
, the data in addresses M
1
-M
4
of the main memory
506
are similarly copied into addresses C
1
-C
4
of the cache memory
504
. The CPU
502
provides respective modified data to the cache memory
504
, whereby the data retained in addresses C
1
-C
4
of the cache memory
504
are rewritten.
At this time point, there is no more empty region in the cache memory
504
. In the subsequent process, data is read out from the main memory
506
into the cache memory
504
after the process of writing the modified data back into the main memory
506
.
At step S
6
, the modified data stored in address C
0
of the cache memory
504
is written back into address M
0
of the main memory
506
. At step S
7
, the data retained in address M
5
of the main memory
506
is read into address C
0
of the cache memory
504
.
At step S
8
, the data stored in address C
1
of the cache memory
504
is written back into address M
1
of the main memory
506
. At step S
9
, the data retained in address M
6
of the main memory
506
is read into address C
1
of the cache memory
504
.
Thereafter, writing back data from the cache memory
504
into the main memory
506
, and reading out data from the main memory
506
into the cache memory
504
are carried out similarly. In this case, data readout and data writing are carried out alternately in the main memory
506
with respect to continuous read and write addresses apart from each other by a constant address.
FIG. 17
shows a schematic structure of a conventional semiconductor memory device.
Referring to
FIG. 17
, a conventional semiconductor memory device
511
receives control signals CS, RAS, CAS, WE, an address signal ADR, and a bank address signal BANK from a memory control device
519
incorporated in a computer system or the like to transfer data DATA.
Semiconductor memory device
511
includes a control circuit
512
receiving control signals CS, RAS, CAS, and WE, address signal ADR and bank address signal BANK to output a row address RA and a column address CA, and also a data input signal DIN according to data DATA, or provides data DATA to memory control device
519
according to a data output signal DOUT read out, a row decoder
513
, a column decoder
514
, an amplify circuit band
516
, and a memory cell array
517
.
Row decoder
513
renders active one of a plurality of word lines WL according to an externally specified row address RA. Column decoder
514
renders active one of a plurality of column select lines CSL according to an externally specified column address CA. A memory cell located at the crossing between activated word line WL and column select line CSL is selected from the memory cell array.
An address signal ADR specifying a word line is provided together with an active command ACT. This address signal ADR is recognized as row address RA. An address signal ADR specifying a column select line is applied together with a read command RD or a write command WRT. This address signal ADR is recognized as column address CA. Read command RD and write command WRT designate reading and writing operations with respect to memory cells of respective specified addresses.
FIG. 18
is a circuit diagram showing a structure of a conventional memory cell array
517
of FIG.
17
.
Referring to
FIG. 18
, each of memory cells Cell00-Cell21 is formed of a capacitor having one end coupled to a cell plate potential Vcp of a constant potential, and a transistor connected to the other end of the capacitor. The transistor is controlled by word line WL, and has the other end connected to a bit line BL or /BL. Sense amplifiers
24
and
44
are provided corresponding to the bit line pair of lines BL, /BL. Also corresponding to the bit line pair are provided transistors
22
and
42
equalizing the potentials of bit lines BL and /BL according to a signal BLEQ. Bit lines BL, /BL are connected to local IO lines LIO, /LIO via select gates
26
and
56
respectively controlled according to column select signals CSL
0
and CSL
1
.
Local IO lines LIO, /LIO are connected to global IO lines GIO, /GIO by a gate circuit
60
rendered conductive by a signal IOSW
0
.
A read amplifier
64
and a write data drive circuit
62
are connected to global IO lines GIO, /GIO. Read amplifier
64
amplifies the potentials of global IO lines GIO, /GIO to output a signal DOUT. Write data drive circuit
62
functions to drive complementarily global IO lines GIO, /GIO according to a data input signal DIN.
Referring to
FIG. 16
again, data is read out from address M
4
of the main memory into address C
4
of the cache memory on a computer having a cache memory (S
5
). The CPU modifies the read out data. The modified data is temporarily retained in the cache memory. Then, data is written back from address C
0
of the cache memory into address M
0
of the main memory (S
6
). Consider the case where data is read out from address M
5
of the main memory into address C
0
of the cache memory (S
7
).
FIG. 19
is an operation waveform diagram to describe the case where access is effected to a main memory employing a synchronous semiconductor memory device (SDRAM).
It is assumed that addresses M
0
, M
4
and M
5
of the main memory correspond to (row address RA, column address CA)=(000, 000), (001, 000), (001, 001), respectively, in FIG.
19
. It is assumed that bank addresses BANK are all 0. Addresses M
0
, M
4
and M
5
correspond to memory cells Cell00, Cell10, and Cell11, respectively, in FIG.
18
.
Referring to
FIG. 19
, command ACT and address “001” are input at time T
1
. Signal BLEQ is pulled down to an L level, and equalization of the bit line pair is canceled. Then, word line WL
1
attains an H level.
Memory cells Cell10 and Cell11 of
FIG. 18
are selected. The data stored in these memory cells are transmitted onto bit line BL. Then, a sens

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