Semiconductor memory device test apparatus

Details Semiconductor memory device test apparatus Semiconductor memory device test apparatus

1980-11-14

1983-11-08

Nusbaum, Mark E.

Excavating

364900, 365201, G06F 1126

Patent

active

044146655

ABSTRACT:
A memory device under test is accessed by an address generated by a pattern generator to write therein data and to read the data out to be compared with expected data, and the comparison result is stored in the fault-address memory by the same address after reading out therefrom the content of the address. When a disagreement is detected through the comparison, it is counted; however, the count operation is inhibited if the data read out from the fault-address memory is a fault data. When the counted number exceeds a predetermined value, a fault signal is generated. After the test is terminated, an address counter is operated, the fault-address memory is read out by the content of the address counter, and when fault data is detected from the output read out, the content of the address counter is fetched into the CPU.

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