Semiconductor memory device suitable for mounting mixed with...

Details Semiconductor memory device suitable for mounting mixed with... Semiconductor memory device suitable for mounting mixed with...

2000-09-05

2001-06-19

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060

Reexamination Certificate

active

06249476

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device suitable for mounting mixed with a logic circuit such as a logic device and a microprocessor. More specifically, the present invention relates to a configuration of a semiconductor memory device for reducing cycle time in a reading operation of a DRAM (Dynamic Random Access Memory) mounted together with logic circuitry.
2. Description of the Background Art
DRAM system LSI (Large Scale Integrated Circuit Device) having a DRAM and a logic device or a microprocessor integrated on one same semiconductor substrate has come to be widely used. The DRAM embedded system LSI is advantageous over the conventional system in which separate DRAM and logic device are soldered on a printed circuit board in the following points.
(1) Consideration of pin terminals of the separate DRAM is unnecessary, and therefore data bus width between the DRAM and the logic can be widened, which leads to improved data transfer rate and hence improved system performance;
(2) A data bus formed on a semiconductor substrate has smaller parasitic capacitance as compared with a line on a printed board, and therefore charging/discharging current of signal line can be reduced, which leads to smaller current consumption at the time of data transfer; and
(3) Single packaging becomes possible, and data bus lines and control signal lines on the printed board can be reduced, so that occupation area on the printed board can be reduced.
FIG. 19
represents an example of a conventional DRAM embedded system LSI configuration.
Referring to
FIG. 19
, in the DRAM embedded system LSI, a logic circuit LG and a DRAM macro are integrated on one semiconductor substrate chip CH.
The DRAM macro includes memory arrays MA
0
and MA
1
each having a plurality of memory cells arranged in a matrix of rows and columns, row decode circuits XD
0
and XD
1
provided for memory arrays MA
0
and MA
1
, respectively, for selecting an address-designated row of the corresponding memory arrays MA
0
and MA
1
, column decode circuits YD
0
and YD
1
provided for memory arrays MA
0
and MA
1
, respectively, for selecting an address-designated column of memory arrays MA
0
and MA
1
, data paths DP
0
and DP
1
for communicating data with the column of memory cells selected by column decode circuits YD
0
and YD
1
, and a control circuit CG controlling data access operation to memory arrays MA
0
and MA
1
.
Data paths DP
0
and DP
1
are coupled to logic circuit LG through data buses DB
0
and DB
1
, and control circuit CG is coupled to logic circuit LG through a control bus CTB. In
FIG. 19
, data buses DB
0
and DB
1
transmit 128 bits of write data and 128 bits of read data separately.
FIG. 20
is a schematic representation of the configurations of memory arrays MA
0
and MA
1
shown in FIG.
19
. Memory arrays MA
0
and MA
1
are generally represented as one memory array MA in
FIG. 20
, as the memory arrays have identical configurations.
Memory array MA includes a plurality of memory cell blocks MCB arranged in a matrix of rows and columns. Though not explicitly shown, memory cells are arranged in a matrix of rows and columns in memory cell block MCB. For each memory cell block MCB, local IO line pairs LIOs for communicating data with the corresponding memory cell block are provided. The pair of local IO lines transmit signals complementary to each other.
Sense amplifier groups SAs are arranged corresponding to respective memory cell blocks MCB. Sense amplifier groups SAs have shared sense amplifier scheme, and shared by memory cell blocks adjacent in the column direction. The sense amplifier groups SAs include sense amplifier circuits SA each provided corresponding to each column of the corresponding memory cell block, for sensing, amplifying and latching data of the address-designated memory cell column when activated. Sense amplifier groups SAs are selectively coupled to the corresponding local IO line pairs LIOs.
Word lines WLs are arranged commonly to memory cell blocks MCB arranged aligned in the row direction. In operation, one word line WL among word lines belonging to one row block (a block consisting of a plurality of memory cell blocks arranged aligned in the row direction) is driven to the selected state.
In an area between memory cell blocks adjacent to each other in the row direction and the area outside the memory cell blocks (these areas will be referred to as interblock areas), global IO line pairs GIO
0
to GIO
127
are arranged extending in the column direction. Four global IO line pairs are arranged commonly to memory cell blocks aligned in the column direction. Four pairs of local IO lines LIOs are arranged for each memory cell block, and four pairs of local IO lines LIOs provided corresponding to each memory cell block MCB in one row block are each coupled to the corresponding global IO line pair through an IO switch IOSW.
Each of the global IO line pairs GIO
0
to GIO
127
transmits mutually complementary signals, and coupled to a data path shown in FIG.
19
and coupled to logic circuit LG through a read/write circuit in the data path.
In the same interconnection layer as global IO line pairs GIO
0
to GIO
127
, a column selection line CSL is arranged extending in the column direction over memory array MA. Column selection lines CSLs are shared by memory cell blocks MCB arranged aligned in the column direction. By IO switch IOSW, local IO line pairs LIOs of the selected row block are coupled to global IO line pairs GIO
0
to GIO
127
, and local IO line pairs LIOs of nonselected row blocks are separated from global IO line pairs GIO
0
to GIO
127
. Therefore, four columns are simultaneously selected in each column block (a block constituted by memory block cell blocks arranged aligned in the column direction), and four local IO line pairs LIOs are coupled to the corresponding global IO line pairs.
FIG. 21
is a block diagram representing arrangements of circuits and flow of control signals related to a reading operation in a conventional DRAM macro.
Referring to
FIG. 21
, difference in access time between data reading from a memory cell connected to a sense amplifier SAf positioned at a farthest point from a control circuit and data reading from a memory cell connected to a sense amplifier SAn positioned at the nearest point on the memory array will be considered.
The sense amplifier SAf at the farthest point is coupled selectively to local IO line pair LIOf by column selection line CSLf, and data read to local IO line pair LIOf is transmitted to the corresponding global IO line pair GIOf. Potential difference generated on global IO line pair GIOf because of the coupling with sense amplifier SAf is amplified by preamplifier PAf, and read data is taken out.
Similarly, the sense amplifier SAn at the nearest point is selectively coupled through local IO line pair LIOn to global IO line pair GIOn, by column selection line CSLn. Potential difference generated on global IO line pair GIOn because of the coupling with sense amplifier SAn is amplified by preamplifier PAn and the read data is taken out.
In the following, signal lines, control signals and circuits having reference characters with a suffix “f” in the specification represent those provided corresponding to the sense amplifier SAf at the farthest point. Similarly, those designated by reference characters with suffix “n” represent those provided corresponding to the sense amplifier SAn at the nearest point.
Control signal CG takes in a read command and an address in synchronization with an external clock in a reading operation, and generates an equalize signal GIOEQ to cause precharge/equalize operation on global IO line pair, a preamplifier activating signal PAE designating activation timing of preamplifier PA, and read predecode signals YA <
3
:
0
> and YB <
3
:
0
> input to the column decoder. Here, each of the read predecode signals YA <
3
:
0
> and YB <
3
:
0
> is a signal

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