Semiconductor memory device row decoder structures having...

Details Semiconductor memory device row decoder structures having... Semiconductor memory device row decoder structures having...

2002-04-11

2003-12-16

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030, C365S189110, C365S189090

Reexamination Certificate

active

06665229

ABSTRACT:

This application claims priority from Korean Priority Document No. 2001-28258, filed on May 23, 2001 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to semiconductor memory device row decoder structures having reduced layout area, and methods of operating the same.
2. Description of the Related Art
Semiconductor memory device is generally classified into the volatile and nonvolatile categories.
Volatile memories perform quick read and write operations, but have the disadvantage of being erased, if an external power supply is cut off. These are further classified into dynamic random access memories (DRAMs) and static random access memories (SRAMs).
On the other hand, nonvolatile memories keep the data stored in the memory cells, even if they lose power. These are further classified into mask read only memories (MROMs), programmable read only memories (PROMs) and electrically erasable and programmable read only memory (EEPROMs).
Nonvolatile memories are mainly used for data that should not be lost if the power supply is lost. A result is that, in case of MROMs, PROMs or EEPROMs, common users are not free to perform erase and write (or program) processes. In other words, it is not convenient to erase or re-program the contents programmed at the on-board state. On the contrary, it is possible for the EEPROM system to perform the electrically erase and write processes in itself. Therefore, the EEPROM has been continuously expanded in the applications to be used as a system program storage device, or an auxiliary memory device requiring continuous renewal of its contents.
In other words, it is highly desirable to develop the EEPROM that can be electrically erasable or programmable at high speed, for a variety of electronic devices that can be controlled by computers or microprocessors. Furthermore, since a relatively large area is taken for a hard disk device having a rotary magnetic disk to be used as an auxiliary memory device in a battery powered computer system at the size of a portable computer or notebook computer, designers of such systems have been greatly interested in development of an EEPROM having both a compact size and a high speed operation.
Accordingly, a NOR type flash EEPROM having a flash erase function, appeared along with the advancement of EEPROM design technology, has been welcomed by users who have demanded a high speed memory device including faster programming, write and read operations than those of NAND type or AND type EEPROM.
Referring now to FIG.
1
and
FIG. 2
, a general structure and a general operation of a NOR-type flash memory device are described.
FIG. 1
shows a vertical cross-section of a memory cell transistor constructing a memory cell unit of a general NOR type flash memory. A n-type source region
3
is formed in p-type substrate
2
(also known as bulk). A n-type drain region
4
(also known as bit line B/L) is formed in p-type substrate
2
. Regions
3
and
4
define a channel between them, which has a thin (less than 100 angstroms) insulating layer
5
on it. A floating gate electrode
6
is formed on insulating layer
5
, over the channel. An insulating layer
7
is formed over the floating gate electrode
6
, and a control gate
8
(which may be called a word line W/L) is formed on insulating layer
7
. A gate voltage Vg is applied to control gate
8
.
FIG. 2
is a table that indicates levels of voltage to be applied to the device of FIG.
1
. These effect different modes of operation, such as program, erase, and read operation modes.
First, the program operation is performed by injection of hot electrons from the drain region
4
and its adjacent channel region to the floating gate electrode
6
. Any injected electrons will remain there, even if the device is turned off, which is why the device is nonvolatile.
As shown in the Table 1, an injection of hot electrons is made by applying a high level of voltage, 10V for instance, to the control gate electrode
8
and an adequate level of voltage, 5-6V for instance, to the drain region
4
for generation of hot electrons while the source region
3
and the p-type substrate region
2
are grounded. When enough negative charges are thus accumulated at floating gate electrode
6
, the memory cell transistor has a higher level of threshold voltage than that prior to the program operation.
Second, the read operation is performed by applying a level of positive voltage, 1V for instance, to the drain region
4
and a predetermined level of voltage, 4.5V for instance, to the control gate electrode
8
while the source region
3
and the substrate region
2
are grounded.
After the program operation, those of the memory cell transistors having a higher level of threshold voltage function as off-cells during the read operation, to prevent current from flowing from the drain region
4
to the source region
3
. In this case, the memory cell transistor is called “an off-cell”. At this time, the programmed memory cell transistors generally have voltage distribution at the range of 6 to 7V.
In the NOR type flash memory cell transistor, the erase operation is performed by generating a Fowler-Nordheim tunneling phenomenon (hereinafter referred to as F-N tunneling) from substrate
2
to control gate electrode
8
. For creating the F-N tunneling, it is required that a high level of negative voltage, −10V for instance, be applied to the control gate electrode
8
, and an adequate level of voltage, 5V for instance, to the bulk region as shown in the table 1. In this case, the drain region
4
is set at high impedance, so that the erase operation is performed effectively. The aforementioned conditions of the erase operation form a strong magnetic field between the control gate electrode
8
and the bulk region, which bring about the F-N tunneling. Accordingly, any negative charges stored in floating gate electrode
6
are discharged to source region
3
. The F-N tunneling is commonly known to happen when the magnetic field of 6 to 7 MV/cm is applied to the conductive layer between the insulating layers. Even in the aforementioned memory cell transistor, the gate insulating layer
7
is formed in the thickness of 100 angstroms to permit the F-N tunneling to happen. As a result of the erase operation, the level of threshold voltage becomes lower at the memory cell transistor, than that of the case that electric charges are accumulated at the floating gate electrode
6
.
During the read operation, the memory cell having the level of threshold voltage lowered by the erase operation functions as an on-cell, because of a current path from a drain region to a source region along the channel. At this time, the memory cell transistor is called an on-cell. The threshold voltage of the erased memory cell transistors is in the range of approximately 1V to 3V.
In the general flash memory, many cells are formed in the bulk region for high integration. Moreover, they are connected, so that they can be erased simultaneously, during the aforementioned erase operation. These cells are also divided in regions, each of which has an erase unit. For instance, a group of memory cells that can be electrically erased as a unit of 64K byte are together called a sector.
FIG. 3
shows a memory cell array in the prior art. In fact,
FIG. 3
is made from FIG.
3
A and
FIG. 3B
, which are considered joined at their common numerals.
In
FIG. 3
, each of the word lines WLi is commonly connected to gates of n memory cells. Each of the bit lines BLi is commonly connected to drains of m cells.
A plurality of unit sectors of 64 K byte are formed, and a core block has a row decoder for selectively driving word lines of the unit sectors. If the unit sector in the memory cell array is of 64 K byte, the number of word lines W/L is generally 1024 and the number of bit lines is 512.
The memory device of
FIG. 3
includes a plurality of sectors
300
-
300
n

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