Semiconductor memory device reading/writing data of multiple bit

Static information storage and retrieval – Addressing – Plural blocks or banks

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Details

36523006, 3652385, 36523001, 365 63, G11C 700, G11C 1134

Patent

active

053696190

ABSTRACT:
A semiconductor memory device includes a memory cell array divided into a plurality of block. In one region on the memory chip, four blocks, two input/output circuits, and two data buses are arranged. In the other region on the chip, four blocks, two input/output circuits, and two data buses are arranged. Each block in each region is divided into two sub-blocks corresponding to the two input/output circuits. Each data bus is connected between the corresponding input/output circuit in the same region and the corresponding two sub-blocks.

REFERENCES:
patent: 4854677 (1989-07-01), Chappell et al.
patent: 4958326 (1990-09-01), Sakurai
patent: 5150330 (1992-09-01), Hag

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