Semiconductor memory device preventing erroneous writing in...

Details Semiconductor memory device preventing erroneous writing in... Semiconductor memory device preventing erroneous writing in...

2002-11-25

2003-06-24

Elms, Richard (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S189011, C365S230060

Reexamination Certificate

active

06584005

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to the circuit structure of a column decoder.
2. Description of the Background Art
Recent mainstream of memory devices is a flash memory (batch-erasable, electrically-rewritable read only memory) which is capable of storing data in a non-volatile manner. Especially, a MONOS (metal oxide nitride oxide silicon)-type memory cell has attracted attention in the field of the flash memory because of reduced costs and smaller area.
The MONOS-type memory cell is different from a floating-gate-type flash memory in that a floating gate formed from polysilicon is replaced with a gate formed from a nitride film capable of trapping charges.
FIG. 19
is a cross-sectional view of the MONOS-type memory cell MC.
Referring to
FIG. 19
, an oxide film
4
, a nitride film
5
, an oxide film
6
, and a control gate
7
are stacked on a P-type semiconductor substrate
1
. Oxide film
4
, nitride film
5
and oxide film
6
are insulating films, and control gate
7
is formed from polysilicon. In P-type semiconductor substrate
1
, N-channel diffusion regions
2
,
3
are formed near the stacked portion in a self-aligned manner.
Bit lines
9
are formed in a layer located above control gate
7
via contact holes
8
electrically coupled to diffusion regions
2
,
3
. Bit lines
9
are formed from a metal layer. Note that this control gate functions as a word line. In order to reduce the electric resistance value of control gate
7
formed from polysilicon, it is also possible to form a metal layer having a low electric resistance value above control gate
7
so as to electrically couple the metal layer to control gate
7
. However, the word line as used in the specification refers to a region of control gate
7
that does not include such a metal layer portion formed above control gate
7
.
Memory cell MC thus corresponds to an N-channel field effect transistor formed on P-type semiconductor substrate
1
. Such a memory cell MC is also referred to as a transistor cell.
In the structure of
FIG. 19
, bit lines
9
are formed in a layer located above control gate
7
via contact holes
8
. However, diffusion regions
2
,
3
may be replaced with bit lines formed from a diffusion layer without using contact holes
8
.
FIG. 20
is a cross-sectional view of a memory cell MC# which is different from MONOS-type memory cell MC in FIG.
19
.
Memory cell MC# is different from memory cell MC in that nitride film
5
serving as a charge storage layer is replaced with a granular-silicon-embedded oxide film
5
# as shown in FIG.
20
. Granular-silicon-embedded oxide film
5
# contains a plurality of granular silicons. This memory cell MC# enables improvement in data holding characteristics and reduction in variation of threshold value in write operation as compared to memory cell MC in FIG.
19
.
FIG. 21
shows a series of relations of applied voltages in write operation, read operation and erase operation of MONOS-type memory cell MC.
FIG. 21
also shows the relation between a bit to be read and a threshold voltage (Vth) of memory cell MC in read operation.
FIG. 22
illustrates write operation of MONOS-type memory cell MC.
Write operation of bit
1
will now be described with reference to
FIGS. 21
,
22
. 0 V is applied to P-type semiconductor substrate
1
, 10 V is applied to control gate
7
, 5 V is applied to diffusion region
2
, and 0 V is applied to diffusion region
3
. Of channel electrons accelerated by a steep electric field in diffusion region
2
of the memory cell, high-energy electrons accelerated to a level equal to or higher than the barrier height of the oxide film are trapped in a region of nitride film
5
located on the side of diffusion region
2
(bit
1
). Such trapping of the electrons raises the threshold voltage of memory cell MC, whereby this region of nitride film
5
is rendered in a write state for storing data “0”. It is herein assumed that bit
1
is “0” when this region of nitride film
5
is in a write state, that is, when electrons are trapped in this region of nitride film
5
, and bit
1
is “1” when this region of nitride film
5
is in an erased state, that is, when no data is stored in this region. The following description will be given on the assumption that data in the write state is “0” and data in the erased state is “1”.
Hereinafter, write operation of bit
2
will be described.
In this case, the voltages applied to diffusion regions
2
,
3
are switched. More specifically, 0 V is applied to diffusion region
2
, and 5 V is applied to diffusion region
3
, as shown in parenthesis in FIG.
22
. In this case, electrons are trapped in a region of nitride film
5
located on the side of diffusion region
3
(bit
2
). Such trapping of electrons raises the threshold voltage of memory cell MC, whereby this region of nitride film
5
is rendered in a write state for storing data “0”. Accordingly, bit
2
is “0” when this region of nitride film
5
is in the write state, that is, when electrons are trapped in this region, and bit
2
is “1” when this region of nitride film
5
is in the erased state.
This MONOS structure traps electrons in non-covalent bonds (dangling bonds) which are distributed in a dispersive manner within nitride film
5
. Using different locations of nitride film
5
(i.e., the regions of nitride film
5
located on the side of diffusion regions
2
,
3
) as electron trapping regions enables implementation of data storage of 2 bits/cell.
FIG. 23
illustrates read operation of MONOS-type memory cell MC.
First, read operation of bit
1
(the region of nitride film
5
located on the side of diffusion region
2
) will be described with reference to
FIGS. 21
,
23
.
0 V is applied to P-type semiconductor substrate
1
, 3 V is applied to control gate
7
, 0 V is applied to diffusion region
2
, and 2 V is applied to diffusion region
3
. For example, when the region of nitride film
5
located on the side of diffusion region
2
is in the write state, that is, when electrons are trapped in this region of nitride film
5
, memory cell MC is not turned ON due to a high threshold voltage (4 V or 4.2 V). Therefore, no current path is formed from diffusion region
3
to diffusion region
2
. As a result, “0” can be read as bit
1
. On the other hand, when the region of nitride film
5
located on the side of diffusion region
2
is in the erased state, memory cell MC is turned ON due to a low threshold voltage (1 V or 1.1 V). Therefore, a current path is formed from diffusion region
3
to diffusion region
2
. As a result, “1” can be read as bit
1
.
Read operation of bit
2
(the region of nitride film
5
located on the side of diffusion region
3
) will now be described.
In this case, the voltages applied to diffusion regions
2
,
3
are switched. More specifically, 0 V is applied to P-type semiconductor substrate
1
, and 3 V is applied to control gate
7
. Moreover, as shown in parentheses in
FIG. 23
, 2 V is applied to diffusion region
2
, and 0 V is applied to diffusion region
3
. For example, when the region of nitride film
5
located on the side of diffusion region
3
is in the write state, that is, when electrons are trapped in this region of nitride film
5
, memory cell MC is not turned ON due to a high threshold voltage (4 V or 4.2 V). Therefore, no current path is formed from diffusion region
2
to diffusion region
3
. As a result, “0” can be read as bit
2
. On the other hand, when the region of nitride film
5
located on the side of diffusion region
2
is in the erased state, memory cell MC is turned ON due to a low threshold voltage (1 V or 1.1 V). Therefore, a current path is formed from diffusion region
2
to diffusion region
3
. As a result, “1” can be read as bit
2
.
Accordingly, bits
1
,
2
can be read by adjusting the voltages to be applied to diffusion regions
2
,
3
. In other words, bits
1
,
2
can be read according to whe

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