Semiconductor memory device preventing a malfunction caused...

Details Semiconductor memory device preventing a malfunction caused... Semiconductor memory device preventing a malfunction caused...

1999-11-12

2001-01-09

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S225700, C365S185230

Reexamination Certificate

active

06172934

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that has a plurality of main word lines and a plurality of sub word lines to which memory cells are connected and that allows memory cells to be hierarchically selected by these main word lines and sub word lines.
2. Description of the Related Art
Conventionally, a semiconductor memory device of this type usually has a configuration shown in FIG.
2
. Referring to
FIG. 2
, a plurality of main word lines
2
run from one end of a memory array to the other end. A plurality of sub word lines
4
are connected to each main word line
2
via sub word decoders
3
which act as selection means
3
. Normally, to select one memory cell
6
from the memory array, an address signal
7
is sent to the memory device. Upon receiving this signal, a main word decoder
1
activates one of main word lines
2
. In addition, the signal is sent to the memory device via a sub word line selection signal line
8
to select a sub word line
4
. Upon receiving this signal, each sub word decoder
3
, which is selection means connected to the main word line
2
, selects one of the plurality of sub word lines
4
. When the main word line
2
is broken at
18
as shown in
FIG. 2
, a fuse
14
at the connection between the main word decoder
1
and the main word line
2
, as well as the fuse in a redundant fuse circuit
9
, is opened during the trimming process which is performed after the wafer check process so that a redundant word line
10
may be used. This allows the redundant fuse circuit
9
to select the redundant word line
10
when the main word decoder
1
selects the main word line
2
which is broken.
A plurality of redundant sub word decoders
11
are connected to the redundant word line
10
and, via a redundant sub word line
13
, a memory cell
12
is selected from the memory array. Therefore, the device may be used as a non-defective device.
When the main word line
2
is broken in the conventional semiconductor memory device described above, a part
19
of the main word line
2
shown in
FIG. 2
becomes a floating contact. The main word line
2
which is broken during operation is broken by the fuse, and a relatively less powerful pull-up transistor
17
keeps the main word line
2
at the low level up to the position where the line is broken. However, beyond the position where the line is broken, there is no means for keeping the electric potential. Therefore, the electric potential of this part of the line, which is coupled with the near wire lines, increases, causing the sub word lines which should not be activated to activate.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention to provide a semiconductor memory device in which sub word lines, which should not be activated when a main word line becomes defective, are not activated.
The semiconductor memory device according to the present invention has a plurality of main word lines and a plurality of sub word lines to which memory cells are connected, one of the plurality of sub word lines being selected for each block on each main word line via selection means, wherein the main word lines are each grounded by a high-resistance resistor.
In addition, multiple points on the main word line may be grounded. The connection between the main word line and the sub word line may be grounded. Also, the main word line may include a redundant main word line, and the sub word line may include a redundant sub word line. In addition, the main word line may be made of aluminum or tungsten.


REFERENCES:
patent: 5436910 (1995-07-01), Takeshima et al.
patent: 5748554 (1998-05-01), Barth et al.
patent: 5848021 (1998-12-01), Subibayashi
patent: 5933387 (1999-08-01), Worley

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