Semiconductor memory device permitting stabilized operation...

Details Semiconductor memory device permitting stabilized operation... Semiconductor memory device permitting stabilized operation...

2000-01-04

2001-06-12

Ho, Hoai V. (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230030, C365S230060

Reexamination Certificate

active

06246633

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device permitting high-speed access operation at a timing of activation of an address buffer, while reducing a stand-by current consumption.
2. Description of the Background Art
In a memory device in which a data signal is transmitted between a selected memory cell and an outside according to an externally supplied address signal, one known technique to reduce current consumption during stand-by is to provide a transmission circuit at an input stage of an address buffer taking in the address signal that is inactivated during stand-by. Provision of such a transmission circuit can prevent generation of an unnecessary through current within the address buffer.
To relax noise in the address signal and to secure margin for write recovery time in a static random access memory (SRAM), a prescribed delay time is added to the externally supplied address signal in an address buffer circuit, and the resulting address signal is applied to an address decoder performing selection of rows and columns of memory cells.
FIG. 11
is a block diagram illustrating a configuration of a conventional address buffer
500
and peripheral circuits thereof, to be used for these purposes.
Referring to
FIG. 11
, n+1 bits of address signal A
0
-An (n is a natural number) are input into address buffer
500
, which in turn transmits each bit of the received address signal to an address decoder
560
.
Address buffer
500
detects transition in signal level of each bit of the address signal, and transmits the information to a global ATD circuit
570
. Global ATD circuit
570
outputs an address transition detecting signal GATD that is activated when the signal level changes in at least one of the bits of the address signal.
Address buffer
500
receives the address signal from address signal input terminals
501
-
0
to
501
-n that are provided corresponding to respective bits of the address signal. Address buffer
500
receives from a node n
101
an address buffer activation signal FACT generated by an address buffer activation circuit
550
. Address buffer activation circuit
550
activates (to an L level) address buffer activation signal FACT in response to the activation (to an L level) of a chip select signal /CS designating activation of the entire memory device.
Address buffer
500
further includes address signal input circuits
510
-
0
to
510
-n that are provided corresponding to respective bits of the address signal. As each address signal input circuit has the same configuration and operates in the same manner, the configuration of address input circuit
510
-
0
provided corresponding to a leading bit A
0
of the address signal will now be described representatively.
Address input circuit
510
-
0
includes an address signal transmission circuit
520
that is activated in response to address buffer activation signal FACT. Address signal transmission circuit
520
is a circuit provided for reducing the current consumption of the address buffer during stand-by.
FIG. 12
is a circuit diagram showing a configuration of address signal transmission circuit
520
.
Referring to
FIG. 12
, address signal transmission circuit
520
includes P type MOS transistors Q
50
, Q
51
, coupled in series between a power supply line and a node N
1
, and an N type MOS transistor Q
52
coupled between node N
1
and a ground line. Transistors Q
51
and Q
52
have gates connected to address signal input terminal
501
-
0
, and transistor Q
50
has a gate connected to node n
101
.
Address signal transmission circuit
520
further includes an N type MOS transistor Q
53
connected between node N
1
and the ground line. Transistor Q
53
has a gate connected to node n
101
. With such a configuration, transistor Q
53
turns on and transistor Q
50
turns off when address buffer activation signal FACT is at an inactive state (of an H level). Thus, address signal A
0
is not transmitted to node N
1
, and the voltage level of node N
1
is fixed at a ground voltage GND (at an L level) by transistor Q
53
.
In contrast, when address buffer activation signal FACT is activated (to an L level), transistor Q
53
turns off and transistor Q
50
turns on. Thus, node N
1
is separated from the ground line, and an inverter formed of transistors Q
51
and Q
52
to which a current is supplied by transistor Q
50
inverts the signal level of address signal A
0
and transmits the inverted state to node N
1
.
The signal level at node N
1
is transmitted to node n
102
via inverters IV
51
and IV
52
.
With such a configuration, it is possible to cut a through current at address signal transmission circuit
520
, regardless of the signal level of address signal A
0
. Furthermore, since the signal level at node N
1
during stand-by can be set in advance, it is also possible to cut the through current at each of post-connected circuits on stand-by without difficulty.
Referring to
FIG. 11
again, address signal input circuit
510
-
0
further includes a delay circuit
530
that outputs to node n
106
a change in voltage level at node n
102
after a lapse of delay time td, and a local ATD circuit
540
that outputs to node n
107
a one-shot pulse that is activated (to an L level) when the voltage level at node n
102
changes.
The voltage levels at nodes n
106
and n
107
are inverted by inverters IV
53
and IV
56
and transmitted to nodes n
103
and n
104
, respectively. Output to node n
103
is a data signal DA
0
that corresponds to the signal level of the input address signal. Similarly output to node n
104
is a one-shot pulse signal LA
0
that is activated (to an H level) when address signal A
0
changes from an H level to an L level or from the L level to the H level.
Delay time td is set by delay circuit
530
such that a sufficient time is guaranteed for relaxing noise of the address signal input to the address input terminals, or for securing margin for write recovery time.
Other address signal input circuits
510
-
1
to
510
-n operate in the same manner, and similarly output signals DA
1
to DAn and LA
1
to LAn. Address decoder
560
generates address select signals AS
0
to ASn for selecting an address corresponding to the signal level given to each bit at each of the address signal input terminals.
Global ATD circuit
570
receives outputs LA
0
to LAn from respective local ATD circuits and, when at least one of the signals LA
0
to LAn is activated, activates address transition detecting signal GATD by adding an appropriate delay time thereto. GATD is a pulse signal activated for a prescribed time period, which detects start of a new access by monitoring switching of the address signal. For example, this signal GATD can be used to control equalization of data lines or the like such that the equalizing operation is completed immediately before the activation timing of word lines. Data reading and writing operations can thus be sped up.
The above-described delay time to be added by global ATD circuit
570
can be adjusted to obtain optimal timing between activation of LA
0
to LAn at local ATD circuits and activation of word lines.
Now, another configuration of conventional address buffer will be described, in the case where it has a byte control function that enables portion-by-portion switching between activation and inactivation of a word configuration to be handled.
FIG. 13
is a block diagram showing a configuration of a conventional address buffer having the byte control function and peripheral circuits thereof.
In
FIG. 13
, the configuration of an address buffer activation circuit
555
is different from that of address buffer activation circuit
550
shown in FIG.
10
.
Referring to
FIG. 13
, address buffer activation circuit
555
receives byte control signals /BC
1
and /BC
2
. The byte control signal is a signal that controls switching between activation and inactivation for every byte, by dividing a word configuration having, for example, 16 bits into 2 byte

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