Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-08-26
2003-11-04
Phung, Anh (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S201000
Reexamination Certificate
active
06643217
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices taking in external signals such as address signals, timing signals and input data in synchronization with an external clock signal, and more particularly to a semiconductor memory device configured to sequentially read out a plurality of pieces of data in synchronization with a clock signal.
2. Description of the Background Art
With advancement of microprocessor units in recent years, speeding of not only the main frame but also the entire computer system of workstation, personal computer or the like has proceeded. Even a system with an operating frequency exceeding 100 MHz is now available by virtue of the advent of a RISC (restricted instruction set computer) processor. A dynamic random access memory (DRAM) used for a main memory of such a computer system or graphics has undergone downsizing as well as speeding year after year. However, technical advances of the microprocessor units have outrun the speeding of the DRAM, and there is an increasing gap in performance therebetween. By way of speeding the DRAM, a synchronous DRAM dramatically improved in data transferring capability has been developed.
The synchronous DRAM is a synchronous type DRAM which performs command latching and data input/output in synchronization with rising edges of a clock signal being input. Such a synchronous type DRAM offers high-speed operation control by synchronizing with a system clock, generally adopting a pipelined circuit configuration.
The pipelined circuit configuration enables a high-speed operation by dividing the circuitry performing a series of reading operations from address input to data output into blocks, and causing the respective blocks to operate in a multiplexed manner in response to the clock signal.
A three-stage pipelined circuit configuration is now described by way of example.
Assume that a first stage corresponds to a time period from input of an address signal to selection of a column switch; a second stage corresponds to a time period from selection of the column switch to latching of read data; and a third stage corresponds to a time period until the read data is transmitted from an output buffer circuit to an output terminal and its level is settled. These stages are separated from each other in accordance with the clock signal to multiplex the internal operations.
For example, in an operation with a clock signal of 100 MHz, initial data is obtained in a time period within 30 ns corresponding to three clock cycles. Thereafter, data of 10 ns each are output sequentially in respective cycles by virtue of the multiplexed configuration. As such, although the time required for an initial access is equal to that of a conventional normal DRAM, the times required for the succeeding accesses are speeded considerably from those of the normal DRAM, so that data transfer rate dramatically increases. In the three-stage pipelined circuit configuration described above, three cycles are required from the input of a column address to the output of selected data, which is generally called CAS latency
3
.
CAS latency indicates the number of clock cycles required from the time when a column address as data read designation is input until the time when valid data becomes ready for output. A column address strobe signal/CAS is utilized as a timing signal for reference, although a row address strobe signal/RAS may be used alternatively.
In the synchronous DRAM, use of a clock signal of an increased frequency is advanced for the purpose of enabling rapid data reading. However, a certain time period is required from the input of a column address to the output of valid data for column select operation, amplification operation and other operations, regardless of the clock frequency.
This means that the CAS latency should be increased to perform data reading using a high-speed clock.
By comparison, a wafer test is generally conducted using a tester which employs a low-speed clock, taking account of the cost. If such a tester of low-speed clock is used for testing a synchronous DRAM designed to conform to a high-speed clock and thus having large CAS latency, it would require a long time from the designation of data reading to the completion of data output, since the synchronous DRAM is a clock synchronous system. In other words, detection of defective test data in the wafer test would take a long period of time.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device which allows early detection of defective test data.
The semiconductor memory device of the present invention includes a memory array storing data, a data output circuit, and a latency setting circuit.
The data output circuit transmits read data output from the memory array to a data output node. The latency setting circuit, in response to designation of a data reading operation, controls the operation timing of the data output circuit and adjusts a data transmission period until the read data is transmitted to the data output node. In a test mode, the latency setting circuit sets the data transmission period shorter than in the normal data reading operation.
Thus, the primary advantage of the present invention is that the data transmission period required for outputting read data from a memory array can be set shorter in the test mode than in the normal data reading operation. This permits reduction of the test time of the read data even in a performance test employing a tester of low-speed clock.
REFERENCES:
patent: 5568445 (1996-10-01), Park et al.
patent: 5966343 (1999-10-01), Thurston
patent: 6151270 (2000-11-01), Jeong
patent: 6327217 (2001-12-01), Chung
McDermott & Will & Emery
Mitsubshi Denki Kabushiki Kaisha
Phung Anh
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