Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2001-11-16
2003-01-28
Lam, David (Department: 2818)
Static information storage and retrieval
Powering
Conservation of power
C365S226000, C365S189090
Reexamination Certificate
active
06512715
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device capable of operating with low power consumption.
2. Description of the Background Art
In recent years, semiconductor memory devices capable of being driven with low power consumption have been demanded for use in applications such as battery-powered portable equipments. In response to such a demand, the semiconductor memory devices have a low power consumption mode (power down mode) in addition to the normal mode in which normal operations such as data read operation and data write operation are required. In the low power consumption mode, most of the internal circuitry is rendered in a standby state in order to reduce the power consumption. Thus, according to an external operation request, the operation mode is switched between the normal mode and the low power consumption mode, whereby the power consumption of the semiconductor memory devices is reduced.
Since operation with a reduced voltage is effective for reduced power consumption, an external power supply voltage level has been increasingly reduced. For example, a 3.3 V-level (3.0 V to 3.6 V) external power supply voltage is used in the conventional general-purpose systems. However, a 2.7 V-level (2.7 V to 3.0 V) or 2.5 V-level (2.3 V to 2.7 V) external power supply voltage has been increasingly used in the systems operating a reduced voltage.
With reduction in power consumption, the power consumption ratio of the internal power supply circuit for generating internal power supply voltages to the entire semiconductor memory device is increased. Moreover, operation with a reduced voltage degrades the power efficiency of the internal power supply circuit. Accordingly, there is a need for a more powerful low power consumption mode in which the internal circuitry receiving the internal power supply voltages is rendered in a standby state in order to reduce not only the overall power consumption but also the power consumption of the internal power supply circuit itself.
In such a low power consumption mode as well, it is desirable that the mode entry can be implemented using an existing control system, i.e., without using a special entry method. Smooth transition to the low power consumption mode and smooth restoration to the normal mode are also desired.
As described above, various levels of external power supply voltages are currently used. In order to design the generalized semiconductor memory devices, the semiconductor memory device must be adaptable to different levels of external power supply voltages. For example, the internal power supply circuit is required to have the ability to maintain uniform control response of the internal power supply voltages even when a different level of external power supply voltage is applied.
Depending on the interface specification, the system incorporating the semiconductor memory device must be adapted to a 1.8 V-level I/O (Input/Output) signal of TTL (Transistor-Transistor Logic) level. Therefore, it is desirable that the signal input circuitry also be capable of receiving different I/O signal levels.
In the case where an operating condition to be applied is fixed in terms of the hardware by mask switching or the like in a generalized semiconductor memory device adaptable to various operating conditions (e.g., external power supply level and I/O signal level), the structure is also required that is capable of easily sensing the fixed operating condition from the outside of the semiconductor memory device.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a semiconductor memory device capable of operating with low power consumption.
It is another object of the invention to provide a semiconductor memory device capable of operating with various levels of external power supply voltages and I/O signals.
It is a further object of the invention to provide, in a semiconductor memory device designed to be adaptable to various operating conditions, a structure capable of easily sensing an applied operating condition from the outside.
In summary, according to one aspect of the invention, a semiconductor memory device having a normal mode and a low power consumption mode includes: an internal circuit for conducting a data read operation, a data write operation and a data hold operation; a first external power supply line receiving a first external power supply voltage; a second external power supply line receiving a second external power supply voltage that is lower than the first external power supply voltage; an internal power supply line for transmitting an internal power supply voltage to the internal circuit; and an internal power supply circuit for receiving the first and second external power supply voltages and producing the internal power supply voltage. The internal power supply circuit includes a reference voltage generation portion for receiving the first and second external power supply voltages and generating a reference voltage corresponding to a target level of the internal power supply voltage, a first current shut-off switch for shutting off an operating current of the reference voltage generation portion in the low power consumption mode, an internal power supply voltage generation portion for keeping the internal power supply voltage at the target level according to comparison between the internal power supply voltage and the reference voltage in the normal mode, and discontinuing its operation in the low power consumption mode, and a connection switch for electrically coupling one of the first and second external power supply lines to the internal power supply line in the low power consumption mode.
Preferably, the connection switch includes an N-channel field effect transistor electrically coupled between the first external power supply line and the internal power supply line, and the first external power supply voltage is applied to a gate of the N-channel field effect transistor in the low power consumption mode.
Preferably, the connection switch includes a P-channel field effect transistor electrically coupled between the second external power supply line and the internal power supply line, and the second external power supply voltage is applied to a gate of the P-channel field effect transistor in the low power consumption mode.
In the low power consumption mode, such a semiconductor memory device can produce the internal power supply voltage without operating the reference voltage generation portion and the internal power supply voltage generation portion, allowing for reduction in power consumption of the internal power supply circuit itself.
Preferably, the semiconductor memory device further includes a mode register for retaining a mode setting that is externally applied with a first command. The mode setting includes designation of whether transition from the normal mode to the low power consumption mode is conducted or not. When the transition is designated in the mode setting, the low power consumption mode is started in response to a second command.
Thus, whether the transition to the low power consumption mode can be conducted or not can be selectively set based on the mode setting by a general mode register.
In particular, the second command is a special command for starting the low power consumption mode.
In particular, the internal circuit includes a plurality of memory cells arranged in a matrix, a plurality of word lines provided respectively corresponding to memory cell rows and being selectively activated, and a plurality of bit lines provided respectively corresponding to memory cell columns and being respectively coupled to the memory cells corresponding to an activated word line. The second command is a refresh command for conducting the data hold operation. After the refresh command is started, the low power consumption mode is started with each of the word lines being inactivated. Thus, transition from the normal mode to
Matsumoto Junko
Okamoto Takeo
Yamauchi Tadaaki
Lam David
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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