Semiconductor memory device operating in low power supply...

Details Semiconductor memory device operating in low power supply... Semiconductor memory device operating in low power supply...

2002-03-27

2003-11-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S188000, C365S185160, C365S226000, C365S154000

Reexamination Certificate

active

06643173

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device suitable for storing in relatively small storage capacity and utilized for a battery-operated portable terminal and the like. More specifically, the present invention relates to a semiconductor memory device utilized for Static Random Access Memory (hereafter, referred to as SRAM) and the like realizing the operation in low power supply voltage and low power consumption.
2. Description of the Related Art
Conventionally, the technology in this field is, for example, described in the following documents:
Shingaku Gihou;
ICD97-52 (1997-6);
Institution of Electronics, Information and Communication Engineers;
Shibata and Morimura: a 1 V-operated 0.25 &mgr;m SRAM macro cell for portable device (pages 1-8)
Recently, the SRAM is widely utilized as a cache memory in such as a large-scale integration (hereafter, referred to as LSI) for a specific use utilized for a mobile terminal and the like. The SRAM utilized as described above needs to be small in size and low in power consumption since the battery limited in voltage (for example, 1.2 V) is used as the power supply. As the power consumption becomes in proportion to the square of the power supply voltage, it is the most effective to lower the power supply voltage for saving the power consumption. However, when the power supply voltage is lowered, the operation speed of an MOS transistor used as one of a field-effect transistor (hereafter, referred to as FET), for example, configuring the SRAM becomes slow. If the threshold voltage of the MOS transistor is lowered in order to making the speed high, the amount of leak current caused by a sub-threshold voltage in standby is increased and the amount of the power consumption also increases at the same time.
To solve this problem, there is presented Multi-Threshold Complementary MOS transistor (hereafter, referred to as MTCMOS) as CMOS-LSI technology capable of being operated in low power consumption (for example, around 1 V) in an active state and low in power consumption caused by the leak current in standby. An example of SRAM configuration in the MTCMOS technology is to be shown as FIG.
11
.
FIG. 11
is a schematic diagram showing an example of SRAM configuration in the conventional MTCMOS technology described in the documents presented above. In this SRAM configuration, a memory cell array
10
is configured by an MOS transistor with high threshold voltage and a peripheral circuit by an MOS transistor with low threshold voltage.
The memory cell array
10
has a plurality of word lines WL and a plurality of bit line pairs comprising a positive bit line BL and a negative bit line pair BL/, to the cross points of which a memory cell
11
for storing data is connected.
The peripheral circuit
20
has a row address decoder
21
connected to a plurality of word lines WL and an input/output circuit
22
connected to a plurality of bit line pairs of BL and BL/. The row address decoder
21
is a circuit decoding an address AD with a plurality of bits transmitted from the outside and a circuit selecting the word lines WL. The input/output circuit
22
has a column address decoder outputting a column select signal Y, that is, a bit line selection signal by decoding an address AD with a plurality of bits transmitted from the outside, turns a readout mode by read enable signal RE as a readout control signal, turns a write mode by write enable signal WE as a write control signal, and reads out or writes data DA with a plurality of bits in the memory cell
11
connected to the bit line pair of BL and BL/ selected by the column select signal Y.
Also in this SRAM configuration, in writing the data DA in a certain memory cell
11
, for example, a word line WL connected to the memory cell
11
is selected by the row address decoder
21
while the bit line pair of BL and BL/ is selected at the input/output circuit
22
, and the data DA transmitted from the outside is written in the memory cell
11
.
In reading out the data in a certain memory cell
11
, for example, a word line WL connected to the memory cell
11
is selected by the row address decoder
21
while the bit line pair of BL and BL/ is selected at the input/output circuit
22
, and the data DA is read out from the memory cell
11
and output from the input/output circuit
22
.
The peripheral circuit
20
is connected to the node of power supply voltage VDD (the voltage is, for example, around 1V) through a switch
23
of the MOS transistor with high threshold voltage. The switch
23
is controlled in turned-off state in standby by using a sleep signal &phgr;S to control the drain of battery (for example, 1.2 V) caused by sub-threshold leak current. It is difficult to adopt the MOS transistor with low threshold voltage to a plurality of memory cells
11
since the power supply cannot be cut off even in standby for maintaining the contents of memory. Further, it becomes necessary to consider the power consumption of a memory cell part in being operated by sub-threshold leak current if the scale of the memory cell array
10
becomes large.
This power consumption problem can be solved by configuring the memory cell part by CMOS and setting the threshold voltage at the MOS transistor high. However, since the power supply voltage VDD becomes lowered and bit line delay increases extremely in reading out, high operation speed cannot be obtained at an operation guarantee voltage (1 V, for example). In view of the operation speed, it is necessary to reduce the threshold voltage of the MOS transistor also in the memory cell.
In order to deal with this problem, the increase of power consumption caused by the sub-threshold leak current can be controlled while keeping the operation speed high by, for example, configuring the memory cell part by two kinds of MOS transistors different from each other in the threshold voltage and by using each MOS transistor properly in each circuit. An example of memory cell part configuration is to be shown as FIG.
12
.
FIG. 12
is a circuit diagram showing an example of the configuration near the memory cell in the conventional MTCMOS technology described in the documents presented above. A memory cell
30
corresponds to the memory cell in FIG.
11
and has a flip-flop comprising two inverters
31
and
32
with high threshold voltage holding data in first and second nodes N
1
and N
2
. An N-channel type MOS transistor (hereafter, referred to as NMOS)
33
for writing with high threshold voltage driven by a potential on the word line WL is connected between the positive bit line BL and the node Ni. An NMOS
34
for writing with high threshold voltage driven by a potential on the word line WL is connected between the negative bit line BL/ and the node N
2
.
A readout-acceleration circuit
35
is connected between the bit lines BL and BL/. The readout-acceleration circuit
35
accelerates the speed of readout operation by promoting the discharge of bit line capacitance and is configured by NMOS
35
a
and
35
b
for reading out with low threshold voltage connected to the bit lines BL and BL/ and by NMOS
35
c
and
35
d
with low threshold voltage driven by a potential at the nodes N
1
and N
2
.
In order not to make the operation speed high but to make the power of the memory cell array
10
low, a virtual ground line VGND is arranged almost in parallel to the bit line BL. The one end of the virtual ground line VGND is connected to the node of ground potential GND through an NMOS
41
with high threshold voltage. The NMOS
41
is driven by two-input NOR circuit
42
with low threshold voltage. Since it is a waste of power to accelerate the writing cycle and the operation speed of non-selected bit line by using the acceleration circuit
35
, the NMOS
41
is turned off and controlled in a floating state when the acceleration operation is not needed by using the NOR circuit
42
to input the read enable signal RE and the column select signal Y. As a result, the wasteful increase of power is controlled.
Nex

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